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This voltage creates a field across the gate oxide, which causes the adjacent P substrate to invert to N-type. 这一电压在栅极氧化物层上产生一个电场，它导致毗邻的P型衬底转变成N型。
At the sub 90nm technology node, the gate oxide thickness is expected to be 12-15 Angstrom. 当半导体结点技术发展到小于90纳米时,栅氧化层厚度将减薄至12到15埃。
With Keithley S900 and TEL-P8 test system, it is applied in the evaluation of gate oxide lifetime of 0.13um process. 本文就已有的测试项目TDDB，根据国外前沿的研究结果，提出了一些新的测试方案，并在C语言的环境下实现算法，结合Keithley S900和TEL-P8测试系统，用于测试0.;13um工艺的栅氧化层寿命。
In this thesis, we are going to discuss the characteristics of DPN nitrided gate oxide. 因此本论文将讨论去耦电浆氮化闸极氧化层之元件特性。
To obtain high performance and low power device, gate oxide thickness shrinkage is a main stream in modern ULSI industry. 摘要:为了达到高性能和低电压之元件，减少闸极氧化层厚度是现代超大型积体电路工业的一个主流。
Abstract： The surfaces of poly-Si thin film and gate oxide of thin film transistors were passivated using N2O/NH3 plasma. 摘要：采用N2O和NH3等离子钝化技术对多晶硅薄膜表面和栅氧表面进行了钝化处理。
Furthermore, N ion-implantation that is used in ultra-thin gate oxide parts and in restraining the diffusion of doped impurity is also described. 介绍了氮离子注入在制备超薄氧化栅极及其抑制掺杂杂质原子特别是硼原子扩散等方面的研究和应用。
The problem is that the gate oxide, which in modern chips is just several atoms thick, is becoming too slim to lay down reliably. 问题是，现代晶片中的闸极氧化层厚度只有几个原子，已经薄到不容易确实放置在晶圆上的地步。
The most important defect in large size ingots is void, which can degrade the gate oxide integrity (GOI), so as to affect the yields and stability of devices and 1C. 大直径硅单晶、硅片中的最重要的缺陷之一是VOID，它会严重影响硅器件、集成电路的生产成品率和性能稳定性。
Chapter 1 is an introduction of DPN nitrided gate oxide experiment. The process flow design, device structure and measurement tool are also introduced to realize this experiment. 第一章将针对使用去耦电浆氮化闸极氧化层之背景以及实验规划做个简介，包含元件的制程内容、元件结构及量测仪器，以注明本实验之过程。
The discussion and analysis of RF reliabilities in this thesis included the hot-carrier damage and the critical gate oxide breakdown of MOS transistors. 而本论文中，对于金氧半场效电晶体的可靠度的讨论则是包含了热载子伤害以及闸极氧化层的崩溃。
The degradation of Idsatcan be ex- pressed as a function of the product of the gate current( Ig) and the num ber of charges injected into the gate oxide ( Qinj) in a simple power law. Idsat的退化可以用函数栅电流 ( Ig)乘以注入的栅氧化层电荷数 ( Qinj)的幂函数表达 .
The scaling limit for gate oxide in VLSI is determined by the direct tunneling leakage current. Further device performance improvement can be obtained by using higher dielectric constant material. 中文摘要在深次微米时代,当元件愈做愈小,氧化层越来越薄时,漏电流增大的问题急需解决,而此时应用高介电材料的来取代传统氧化矽便愈发重要。
It is worthwhile to notice that the minimum noise figure increases dramatically after hard oxide breakdown (HBD).It can be explained by the additional shot noise source in gate oxide after HBD. 值得注意的是金氧半场效电晶体在氧化层崩溃后会在氧化层区产生额外的散粒杂讯,因此其最小杂讯值会剧烈地增加。
Hot carrier injection (HCI) test of the MOSFET devices, electron migration (EM) test of the metal interconnects and gate oxide integrity (GOI) test are the most popular WLR test items. 半导体集成电路的晶圆级可靠性的主要测试项目包括MOS器件的热载流子注入测试、栅氧化层完整性测试以及金属互连线的电迁移测试。
A man appeared at the castle gate in the guise of a woodcutter. 一个男子打扮成樵夫的模样出现在城堡的门口。
Gate Oxide Breakdown Mechanism Research 栅氧击穿机理研究
Did you remember to padlock the gate? 你是否记得用挂锁把大门锁上？
How can you get rid of this oxide coating? 你们该怎样除去这些氧化皮？
I saw him make by the gate on his bicycle. 我看见他骑自行车从大门旁边过去了。