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- A 12-bit, 40MS/s pipelined ADC is designed in this paper. 本课题设计了一个12位、40MS/s流水线ADC。
- This thesis describes the system design of a high-resolution pipelined ADC. 本文论述了高速高精度流水线结构模数转换器的设计。
- A 10 - bit 20Mps pipelined ADC is designed, which has the merit of high speed and high resolution. 设计 10位 20MpS 流水线模数转换器,它具有高速度高分辨率的优点。
- The layout design of the proposed pipelined ADC has been finished and the test chip is being implemented. 设计的模数转换器在0.;6um工艺下全部电路运行功耗仅为49mW;比同类电路的平均功耗要低13%25;实现了低功耗的设计。
- In this thesis, a low power 12bit 80MS/s pipelined ADC is designed in TSMC 3.3V 1P5M 0.25um CMOS process. 本文基于TSMC 3.;3V 1P5M 0
- Abstract: The design of a low-voltage, high-speed operational amplifier is based on the pipelined ADC. 文章摘要: 本文设计了一种基于流水线ADC系统应用的低电压、高速运算放大器，该运放使用折叠式共源共栅结构、稳定的电压偏置电路、新型的共模反馈电路，使运放达到更高的性能。
- We wish to design a 1.2V 10-bit 250MS/s ADC, thus, a time-interleaved pipelined ADC architecture is chosen. 在此希望设计一个操作在1.;2V，线性度为10且转换速度在每秒两亿五千万次取样频率的类比数位转换器。因此架构采用时间交错式的管线式类比数位转换器。
- This thesis verifies and implements a specific digital calibration algorithm using a 12-bit, 40MS/s pipelined ADC. 本课题采用12位、40MS/s流水线结构的ADC验证并实现了一种数字校准算法，该算法将流水线ADC的级间闭环运放（仅关键的一个）用简单的开环运放代替，然后在后台根据后台信号的统计规律对开环运放带来的误差进行数字校准。
- Chapter 1 reviews the pipelined ADC architecture and introduces the errors in pipelined ADC. 在第一章中，将介绍管线式类比数位转换器的架构，并讨论由电路非线性对转换器造成的错误。
- This article simply introduced basic operating principle of the pipelined ADC, then discussed and analyzed its error reason one by one. 本文简单介绍了流水线ADC的基本工作原理，然后详细讨论了其产生误差的原因并逐一分析。
- Here, we use a DLL-based clock generator with nonoverlapping circuit to generate three nonoverlapping phases used for capacitor error-averaging in pipelined ADC. 在本论文中，我们利用延迟锁相迴路加上相位非重叠电路来实现一个三相非重叠电路，以供给管线式电容平均容错之类比数位转换器。
- In this thesis, we describe the implementation and measurement results of a 6-bit pipelined ADC with open-loop residue amplification and digital self-calibration. 在这篇论文中，我们描述了一个辅以数位自动校正之开迴路残值增益六位元管线式类比数位转换器的实现与量测结果。
- A low power 10 bit/50 MHz pipeline ADC was designed. 介绍了一种50 MHz,10位,5V流水线模数转换器的设计。
- A 33 MSample/s, 10 bit, 3.3 V pipeline ADC is presented. 介绍了一个 33MHz;10bit;3 3V流水线结构的模数转换器 (ADC) .
- This paper designs a 10b pipelined ADC(1.5b/s) and simulates it with SIMULINK tools from MATLAB.The simulation model of 1.5b per stage is set up and packaged in a module,and then the nine stages are connected to establish the system model. 使用了MATLAB提供的SIMUL INK工具箱;对1.;5位/级10b流水线结构模数转换器系统进行了设计及系统仿真。 用SIMUL INK建立起每级的仿真模型;并将其封装成一个模块;然后把9级模块级联起来;建立起系统的模型。
- System Level Simulation of Pipelined ADC 流水线ADC的系统级仿真
- Analysis nonideal factors in pipeline ADC and put forward some methods to decrease these nonideal factors. 对流水线ADC中的非理想因素进行系统分析，提出了降低非理想因素的方法。
- An Improved Pipelined ADC Architecture 一种改进的流水线模数转换器结构
- The thesis designs a 12 bit 100MS/s pipeline ADC, mainly the structure of the ADC, the sample/hold circuit, the sub-ADC of each level, the MDAC and the digital correction circuit. 本文研究设计了一个精度为12位，采样频率为100MHz的流水线ADC，主要内容包括ADC中总体结构的设计、采样保持电路、各级子ADC、乘法模数转换器（MDAC）、 数字校正电路等主要单元的设计。
- In addition, the development of CMOS technology, including the smaller feature size and lower power supply, brings new obstacles to design the circuits of pipelined ADCs. CMOS工艺的飞速发展，使特征尺寸不断减小和电源电压不断降低，同时也对流水线ADC的电路结构设计提出了许多新的课题。
