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This paper introduces the history of the GPU firstly, and then it analyses the pipeline architecture of GPU. finally, it introduces several types of program languages of GPU. 本文首先介绍了可编程图形硬件的发展，然后分析了它的流水线结构，最后介绍了几种最新的编程语言。
This ADC adopts 9 stage , 1.5bit/stage pipeline architecture, with 10 bit resolution and speed no less than 20MS/s, implemented in CSMC 0.60um DPDM CMOS process. 本文设计的是10位20MHz流水线结构的模数转换器;设计基于CSMC 0.;6um CMOS混合信号工艺。
The other is the ACN algorithm proposed by Babu et al, which belongs to the MEP methods and uses a pipeline architecture, so it is highly modular and parallel, and requires O(M~2) operations. 另一算法是Babu等人提出的属于修正特征值问题的ACN算法,该算法使用流水线结构进行并行运算,每次迭代所要求的计算复杂度为O(M~2)。
To improve the Web performance of homemade server operating system. Kylin, the article designs and implements a novel kernel Web server, KETA, with a software pipeline architecture. 为进一步提高国产服务器操作系统Kylin的Web服务性能,本文设计并实现一种新型基于软流水的内核级Web服务器。
Furthermore, an efficient pipeline architecture designed for PLS algorithm, which is hybridized with our proposed algorithm, is discussed in this thesis and is implemented in our experiments. 甚者，适合在与此演算法搭配的预测性行搜寻的管线式硬体架构也在这篇论文中被提出,并应用在实验中。
A Pipeline Architecture for High Speed FIR Filters 高速FIR滤波器的流水线结构
As a result of adopting pipelined architecture, the processing speed is improved and the operations including calculation and reading/writing of storage harmoniously. 采用流水的方式提高了系统的处理速度，使计算与存储器读／写等操作协调一致；
Radix-4 pipelined architecture is adopted for 16 and 64 points computation.Two-dimensional architecture is adopted for 256 and 1024 points computation . 16,64点运算采用基-4级联流水线结构,256,1024点采用二维结构,数据采用块浮点表示。
The method was simulated by MATLAB, showing the algorithm met the requirement of rounding method and applied to the pipelined architecture of various bits. 提出了改进算法的简化结构，并作了分析。利用MATLAB完成了算法仿真，证明该算法满足舍入式的要求，且适用于任何位数的流水线结构。
Improvement on CORDIC Pipeline Architecture in FFT Design CORDIC流水线结构在FFT设计中的改进
A Low Power 33MSample/s, 10 Bit Pipeline Architecture ADC 低功耗33MHz采样频率,10比特流水线结构的模数转换器
Recently they have laid an underground pipeline. 最近他们铺设了一条地下管道。
This paper is dedicated to the description of design and implementation of a high speed and real- time FFT processor with FPGA. Synchronously pipelined architecture which is based on FFT algorithm of Radix 2 is utilized to achieve high throughput. 本文在分析了基-2FFT算法的基础上,采用同步流水线结构,利用现场可编程门阵列(FPGA)完成256点16位复数点FFT。
This paper porposes a pipelined architecture for implementation of DDC on FPGA, which, based on CORDIC algorithm, can save considerable hardware resources and improve the speed performance as well. 文中提出了一种基于流水线CORDIC算法的数字下变频实现方案,可有效地节省FPGA的硬件资源,提高运算速度。
He obtained a diploma in architecture. 他获得了建筑学的学位证书。
In this thesis, both fundamental and practical limitations to the supply voltage in CMOS ADCs are examined, and techniques to allow low voltage operation of the pipelined architecture are described. 在这本论文当中，对于电源供应在互补式金氧半类比数位转换器在理论和实现上的限制都有所解释，以及描述了导管式类比数位转换器能够操作在低电压的技术。
New laws to deal with this abuse are in the pipeline. 正在制定处理这种弊端的新法令。
The architecture of this house is very substantial. 这座房子的结构很牢固。
The new house he bought was colonial architecture. 他新买的房子是美国初期的建筑。
Without any other additional circuit, the algorithm achieved a pipelined architecture of rounding method by adjusting the quantization level, the quantization error ranged from -1/2LSB to 1/2LSB. 该算法在不附加任何额外电路的情况下，通过对模拟量化比较电平的调整，实现了舍入式流水线结构，其量化误差范围在-1/2LSB与1/2LSB之间。

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