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- low k dielectric layer 低k介质埋层
- FSG, as one kind of low k dielectric film, is very similar with SiO2 in structure and deposition, and can be well used in 0.18-0.13um ULSL. 氟掺杂的氧化硅玻璃(FSG)作为低介电常数材料的一种,它的制备工艺、结构和性能更接近二氧化硅,足以满足0.;18微米甚至0
- NTBI induced device degradation can be suppressed by a SiN capping layer between Poly-Si gate and high k dielectric layer. 在闸极与高介电常数介电层间使用氮化矽可有效抑制负偏压温度不稳定性的现象。
- This paper introduces basic technology of copper interconnect, including single and dual damascene technology, CMP technology, low k dielectric materials, barrier materials and reliability of copper interconnect. 文中介绍了基本的铜互连布线技术 ,包括单、双镶嵌工艺 ,CMP工艺 ,低介电常数材料和阻挡层材料 ,及铜互连布线的可靠性问题
- The synthesis, structure, properties and process interaction of low k dielectrics are reviewed.Characterization techniques for low k dielectric films are summarized. 综述了低介电常数介质薄膜的制备方法、结构与性能表徵、工艺兼容性等领域的最新进展。
- P. S. Ho, Low k Dielectrics For Submicron Interconnect Applications, Low k tutorial Taiwan, May, 2000 苏子渊;“含有不同烷基团大小之聚醯亚胺与氟化聚醯亚胺的基本性质研究”;中原大学化学工程学系硕士论文;p.;9-16;2000
- Dual damascene technology of Cu / low dielectric layer is introduced in this paper, andthis technology has been used in manufacturing DRAM and logic devices. 介绍了铜/低介电常数介电层的双嵌入式工艺,该工艺已大规模应用于动态记忆存储器(DRAM)和逻辑电路器件中。
- Dual damascene technology of Cu/ low dielectric layer is introduced in this paper, andthis technology has been used in manufacturing DRAM and logic devices. 介绍了铜/介电常数介电层的双嵌入式工艺,该工艺已大规模应用于动态记忆存储器(RAM)逻辑电路器件中。
- High k dielectric HfO 2 films were deposited on p type Si(100) substrates by e beam evaporation. 使用高真空电子束蒸发在p型Si(1 0 0 )衬底上制备了高kHfO2 薄膜 .
- The equivalent oxide thickness (EOT) of an HfO_2 high k dielectric is extracted in two steps. 分两步提取了HfO2高k栅介质等效氧化层厚度(EOT).
- The material, utilized as high- k dielectric, contains hafnium, there is no other information about it. 这些材料,利用高k电介质,包含铪,没有任何其他信息。
- A key problem in chip fabrication is that the new polish method for electromigration and ultra-low K dielectric and Cu electroplating level. 电迁移问题和集成超低k电介质材料与Cu镀层的新抛光方法是芯片制造中的一个关键问题。
- Low dielectric constant ( low k ) films used as intermetal or interlevel dielectrics can minimize interconnect resistancePcapacitance ( RC) delay,power consumption and cross talk of ULSI. 用低介电常数介质薄膜作金属线间和层间介质可以降低超大规模集成电路(ULSI) 的互连延迟、串扰和能耗。
- When an inhomogeneous plane wave is introduced into a dense dielectric layer, it can bounce between the two boundaries. 把一非均匀平面波引进折射率较高的介质层时,它会在上下界面间来回地“弹”射。
- Low dielectric constant (low k) films used as intermetal or interlevel dielectrics can minimize interconnect resistance/capacitance (RC) delay, power consumption and cross talk of ULSI. 摘要用低介电常数介质薄膜作金属线间和层间介质可以降低超大规模集成电路(ULSI)的互连延迟、串扰和能耗。
- Low dielectric constant(low k) films used as intermetal or interlevel dielectrics can minimize interconnect resistance/capacitance(RC) delay,power consumption and cross talk of ULSI. 用低介电常数介质薄膜作金属线间和层间介质可以降低超大规模集成电路(ULSI)的互连延迟、串扰和能耗。
- Tunneling allows voltage to flow from the control gate to the floating gate through the dielectric layer of oxide which separates them. 允许从隧道流电压控制的浮动栅栅绝缘层氧化物通过分隔他们。
- Second,an approach using flat-band capacitance is demonstrated for extracting the EOT of a high k dielectric,without the effects of inversion or accumulation capacitance. 其次;给出了一种利用平带电容提取高k介质EOT的方法;该方法能克服量子效应所产生的反型层或积累层电容的影响.
- Abstract: Low dielectric constant ( low k ) films used as intermetal or interlevel dielectrics can minimize interconnect resistancePcapacitance ( RC) delay,power consumption and cross talk of ULSI. 摘要: 用低介电常数介质薄膜作金属线间和层间介质可以降低超大规模集成电路(ULSI) 的互连延迟、串扰和能耗。
- Especially, the quality of gate dielectric layer determines the reliability and electrical performance of ultra large scale integrated (ULSI) circuit. 特别是闸极介电层的品质能决定ULSI电路的稳定度与电特性表现。