high voltage interconnection

• 高压互连线

high voltage interconnection的用法和样例：

例句

1. Interconnection delay has become a dominant factor in IC design.
   互连线时延是集成电路设计中非常重要的影响因素。
2. A circuit analysis method for VHSIC system considering interconnection effects is presented in this paper.
   摘要给出了高速集成电路系统在考虑互连线效应时的一种电路分析方法。