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- The arrow diagram does not indicate critical path. 箭线图表不注明主要的路径。
- Critical path and critical activities: time management principles. 关键路径与关键作业的权衡之道:时间管理法则。
- Explain the strengths and weaknesses of critical path analysis. 解释关键路径分析的优缺点。
- This thesis estimate the delay of the critical path of an improved floating-point fused multiply-add (MAF) at a qualitative level, and compare it with the basic MAF implementation. 摘要针对一种改进的浮点乘加器结构，对关键路径的延时进行定量的估算，并将其与传统乘加器结构的延时进行比较。
- In typical case, the delay of critical path is 1.38ns, power dissipation is 45.3mW, and layout area of the ALU is 0.05112mm2. The design achieves the goal of higher speed, lower power dissipation and smaller area. 三、典型条件下;所实现版图关键路径延时1.;38ns;平均功耗45
- Simulation shows that the algorithm can obtain less cost and mean path delay, it also has low time complexity. 仿真结果表明,该算法得到的多播路由树具有较小的费用,平均路径延迟也比较小,并且避免了其它同类算法的高复杂性。
- Show the critical path for your project to quickly find problem tasks. 显示项目的关键路径:以快速查找有问题的任务。
- Identifying and discuss critical path items on each job before mobilization. 动员进厂之前,辨别并讨论每项工作的关键路径项。
- Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. 最后，我们提出一个利用路径延迟惯性原理，来测试系统电路连线之串音障碍的新测试方法。
- On our most projects Critical Path Method( CPM) is used for scheduling. 在我们的大多数工程项目中都采用“统筹法”（关键路线方法，简称CPM）排计划。
- Asynchronous design is very sensitive to path delay and is therefore not robust. An example of asychronous circuit is the SR latch which uses combinational feedback. 使用完全同步设计。异步设计对路径延迟非常敏感,因此不很可靠。异步电路的一个例子是使用组合反馈的。
- This produces a maximum path delay, which is the delay between two DTEs of 400 meters, plus the repeater delay of one repeater instead of four repeaters. 这样就产生了一个最大路径迟延，也就是两个DTE之间的400米迟延，另外一个中继器的迟延取代了四个中继器的迟延。
- The critical path method was originally developed to solve scheduling problems in an industrial setting. 关键路线方法最初的发展是为了解决一项工业安装的安排问题。
- The key is whether you are sticking to the "critical path" when you organize your time, work space, and goals. 关键是当你安排自己的时间、工作范围以及工作目标时，你是否坚定不移地走在一条“至关重要的道路”上。
- The key is whether you are sticking to the critical path when you organize your time,work space,and goals. 关键是当你安排自己的时间、工作范围以及工作目标时，你是否坚定不移地走在一条“至关重要的道路”上。
- Use fully synchronous design. Asynchronous design is very sensitive to path delay and is therefore not robust. An example of asychronous circuit is the SR latch which uses combinational feedback. 使用完全同步设计。异步设计对路径延迟非常敏感,因此不很可靠。异步电路的一个例子是使用组合反馈的SR闭锁。
- To delivery, and as a consequence puts test activities unnecessarily on the critical path of the project. 交付而完成测试准备,并且作为将不必要的测试活动放在项目的关键路径上的结果。
- MCNC(microelectronics centre of north-carolina) standard cell benchmarks are experimented and the results show that the algorithm can make the longest path delay improvement up to 31%. 对MCNC标准单元测试电路中组合和时序电路的实验结果显示;电路经过时延驱动优化布局后的最大路径时延最多减少了31%25.
- Follow-up the critical path of establish of the overall long and short term goals, objectives and priorities needs. 跟进所有短期和长期进度表以满足工作目标和需要。
- This article discusses how to generate robust tests for path delay faults by improving the matured test generation algorithm for stuck at faults, according to the characteristics of path delay faults. 探讨如何利用针对固定型故障测试产生的比较成熟的算法，结合时滞故障的特点，进行路径时滞故障的强健测试产生。
