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- VLSI circuits can contain millions of transistors. 第一块集成电路是1959年由德州仪器公司发明的，在一块半导体表面上只含有6个晶体管。
- Test is an indispensable task of VLSI circuits design. 测试是超大规模集成电路(VLSI，Very Large Scale Integration Circuits)设计中不可缺少的重要环节。
- Glassey, C. R., and M. G. C. Resende. "Closed-Loop Job Release Control for VLSI Circuit Manufacturing." IEEE Transactions on Semiconductor Manufacturing 1, no. 1 (February 1988). 着，“设备效率与设备产能的封闭回路测量”半导体制造IEEE会刊第10卷第1号（1997年二月）
- This study offers a theoretical basis and noise detection method for VLSI circuit components selection, faults diagnosis and localization, and reliability analysis. 这一研究将为VLSI电路器件的严格筛选、故障诊断及定位、VLSI电路的可靠性研究提供新的理论依据和检测方法。
- Glassey, C.R. and Resende, M.G.C., “Cloased-Loop Jop Shop Release Control for VLSI Circuit Manufacturing”, IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 1, pp. 26-46, 1988. 黄宏文，“晶圆制造厂生产活动控制策略之构建”，国立交通大学工业工程与管理学系硕士论文，1995年。
- A method for threshold selection and decision to obtain noise characteristics in VLSI circuits was presented. 摘要给出了利用阈值选取和决策对VLSI电路噪声特性进行检测的方法。
- Boundary-scan technology (BST) is a new and effective way of test and design-for-testability (DFT) for VLSI circuits. 摘要边界扫描技术是一种新型的VLSI电路测试及可测性设计方法。
- An improved algorithm for VLSI circuit partitioning 一类超大规模集成电路分割算法的改进
- Accordingly, this phenomenon also must be taken into account when dealing with VLSI circuits, such as microprocessors or memory devices. 诚然，面对VLSI电路，这种现象同样必须加以考虑，如微处理器或存储器。
- The detailed numerical simulation results of time delay and cross talk noise for the interconnect in VLSI circuits are given. 用数值计算方法详细地模拟了VLSI电路中金属互连线的延迟及串扰。
- Functional Test Generation for VLSI Circuit VLSI电路功能测试码的生成
- As the complexity of VLSI circuits and their quality requirements are increasing, theproblem of test generation is becoming more important and more difficult. 随着VLSI 电路的复杂度越来越高,对其质量要求也越来越高,因此测试生成问题也就变得更加重要,同时也变得更加困难。
- It details the IC design process and VLSI circuits, including gate arrays, programmable logic devices and arrays, parasitic capacitance, and transmission line delays. 它详细规定了集成电路设计过程和超大规模集成电路电路，包括门阵列，可编程逻辑器件和阵列，寄生电容，及输电线路的延误。
- In addition, the algorithm can be realized high speed and low complexity VLSI circuits, without using multiplier, need only shifter, multiplexer and adder. 另外，该演算法已达成高速率和低复杂度的VLSI电路实现，不须要用到乘法器，仅须移位器、多工器和加法器。
- This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep sub-micrometer VLSI circuits. 摘要提出了用来评估深亚微米VLSI电路中RLC互连延时的一种新的解析延时模型。
- VLSI Circuits and Systems ? 超大规模集成电路与系统
- There are two breakers in this circuit. 这个电路里面使用了两个断路器。
- Failure mechanisms, such as hot-carrier effect (HCE), dielectric breakdown, electro-static discharge (ESD) and electromigration, pose serious threat to the long-term reliability of VLSI circuits. 热载流子效应(HCE)、电介质击穿、静电放电,以及电迁移等失效机理,已经对VLSI电路的长期可靠性造成了极大的威胁。
- A replaceable printed circuit board. 一种可替换的印制电路板。
- Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. 摘要 本研究目的乃在发展一套大区域的非破坏检测的振波技术来找出管路中的缺陷或裂缝。
