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- A 600 MHz ECL Programmable Frequency Divider 一种600 MHz ECL高速程控分频器的设计
- A High-Speed ECL Programmable Frequency Divider 一种ECL高速可编程分频器
- The Development of an ECL Programmable Frequency Divider 一种ECL可编程分频器的研制
- Design of a High-Speed Pulse Swallow Programmable Frequency Divider and Its PSPICE Simulation 高速吞脉冲程序分频器的电路设计与PSPICE模拟
- A RESEARCH AND DESIGN OF DIGITAL AND PROGRAMMABLE FREQUENCY DIVIDER CARD BASED ON PC 基于PC机的数字程控分频器卡的研究与设计
- programmable frequency divider 可编程分频器
- N is the desired noninteger frequency divider. N为所要求的非整数分频值。
- It was used as a frequency divider and no numbers are decoded from it. 它被用作无解码输出的分频器。
- Verilog HDL design of frequency divider in RTC module is studied here. 文中研究在RTC模块中分频器设计的Verilog HDL实现。
- This paper gives out a design of the equal duty ratio arbitrary integer frequency divider based on FPGA. 给出了一种基于FPGA的等占空比任意整数分频电路的设计方法。
- Enter button. This button is used to program frequencies in memory. 确认按钮,用来对已编程的频率记忆,了解编程操作更多的信息请参看编程模式相关章节。
- Two pulse outputs, one for active power and the other selectable between reactive and apparent power with programmable frequency. 两路脉冲输出,一为有功功率,二为无功率或视在功率,带频率编程功能。
- Additionally, a highly precise coder on the shaft is researched.A simple and effective frequency divider is designed for correlative calculation. 此外，文中还对高精度码盘在伺服系统中的应用展开了深入的研究，并设计了一套简单实用的分频器以便进行相关的运算。
- The key building blocks in the frequency synthesizer are the voltage controlled oscillator (VCO) and the high frequency divider circuit. 摘要:压控振荡器与除频器是频率合成器电路中，主要的电路之一。
- A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider. 摘要提出了一种基于共振隧穿二极管的新型边沿触发D触发器并将之用于构成二进制分频器。
- Logarithmic sweeps can be performed with a programmable frequency marker signal. Programmable burst count and gating allow you to further customize your signal. 带有可编程频率标记的线性和对数扫频信号,可编程的脉冲列计数和选通能使您进一步自定义信号。
- Other than VCO, the frequency divider is the design bottleneck for high-frequency PLL since the conventional flip-flop based structure is not suitable for high-speed operation. 除压控振荡器外，除频器是另一实现高频锁相迴路之设计瓶颈。
- Voltage controlled oscillator (VCO) and frequency divider (FD) are the main components of phase locked loop (PLL). For VCO, low phase noise can avoid the affection of Adjacent-Channel Interference. 摘要:压控振荡器与除频器是锁相迴路中，主要的电路之一。对压控振荡器而言，低相位杂讯可避免造成相邻通道的干扰。
- This paper introduces the principle of the frequency division and presents the circuit design of the decimal frequency divider based on FPGA. The VHDL language is used for the programming. 摘要介绍了一种基于FPGA的小数分频器的分频原理及电路设计，并用VHDL进行编程实现，并对这种小数分频器的抖动进行分析和计算。
