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master clock generator 主时钟发生器
The Processer Clock is the Master Clock. 请教高手：处理器时钟，主机时钟，外设时钟的关系？
Screening Tests on master clock culture medium of Agrocybe aegerita(Brig.)Sing. 杨树菇母种培养基筛选试验
The level difference of these re-sults at SO is a main reflection of the level difference of UTC master clock. So结果的水平差异主要是协调世界时主钟水平差异的反映；
Can be used in the synthesis loop vibration, high-precision clock generator and FSK / / 3PSK modulation. 可用于本振合成回路，高精度时钟发生器和FSK／／3PSK调制。
And finally, a clock generator based on the 3rd order CPPLL is fully designed with UMC 0.25 CMOS process. 最后，采用UMC 0.;25 CMOS工艺技术设计了一个用作时钟产生的三阶电荷泵锁相环。
In chapter two, a three nonoverlapping phases clock generator is presented at first and the experimental results are given finally. 在第二章中，一各三相非重叠电路将会被提出，而其实验结果将会被论述在本章之末。
The dissertation describes the principle of spread spectrum clock generator and its implement structure.Especially analyzes PLL and the loop divider. 本文先介绍了扩谱时钟发生器（SSCG）的基本原理以及扩谱时钟的不同实现电路结构，并对扩谱时钟发生器中的锁相环（PLL）以及环路分频器进行了分析。
The whole AFE circuit includes a bias circuit, a clock generator, a chopper stabilization amplifier, a post-amplifier, and a second-order continues-time low-pass filter. 本文所提整体类比前端电路包含偏压电路、时脉产生器、截波稳定型放大器、后置放大器、和二阶连续时间低通滤波器。
First, in order to analyze the PLL clock generator, we have established the loop parameters.The parameters effect on the PLL transient characteristic has been studied. 首先，为了分析锁相迴路时脉产生器，我们建立了迴路的参数并探讨这些参数对锁相迴路暂态响应的影响。
The normal idea to make up a digital controled oscillator (DCO)of the digital phase locked loop (DPLL)is to delete the pulses unwanted It need that the master clock frequency must be more faster than the output frepuency of the DPLL. 传统的数字锁相环 (DPLL)多采用吞脉冲的方法来实现DCO ,此方法要求工作频率远高于DPLL的输出频率。
The master clock can be asynchronous with PCM data side clock or ADPCM data side clock. Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的；
The master clock can be asynchronous with PCM data side clock or ADPCM data side clock.Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的；
This essay mainly introduced electric time synchronous net-form mode,the basic concept and the determinant of GPS system.The basic technical need of substation GPS master clock is briefly summarized. 主要介绍了电力时间同步组网模式、GPS系统的基本概念及其决定因素,并对变电站GPS主时钟的基本技术要求作了简短小结。
The ADM system mainly includes a oscillator, a clock generator, an amplifier, a pre-amplif ier, a comparator, an AGC(Automatic Gain Control), an ADM analyzer &synthesizer, a D/A converter and a lowpass filter. 整个系统包括：内置振荡器，时钟产生器，放大器，前置运算放大器，比较器，AGC(自动增益控制器)，ADM分析综合器，数模转换器以及低通滤波器。
Finally, the experimental data for the LNA and the clock generator prototypes are presented to demonstrate the functionalities and performances of the proposed circuit architectures. 最后，本论文呈现低杂讯放大器与时脉产生器电路晶片的量测结果，藉以验证所提出电路架构的弁鄐峈穛{。
A263X integrated features include: optical sensor array, DSP, USB transceiver, PS/2 transceiver, clock generator, voltage regulator and support for latest Windows Vista tilt-wheel function. A263X系列的主要特点包括：光学传感器阵列；DSP数字信号处理器；USB收发器；PS/2收发器；时钟发生器；
The ADC aperture jitter must be minimal, and the sampling clock generated from a low phase-noise quartz crystal oscillator. ADC的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。
This thesis presents the CMOS design and implementation of the low noise amplifier (LNA) and clock generator circuits, the most critical parts of the analog front end in a UWB transceiver. 本论文探讨使用CMOS制程设计与实现两个位于超宽频接收机类比前端最重要的电路，分别为低杂讯放大器与时脉产生器电路。

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