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- instruction level power model 指令级功耗模型
- What is more,this power model can also be utilized as a testing platform for system level and software level power estimation research. 同时,此功耗评估模型也可以作为高层功耗优化研究的测试平台,为系统级、软件级功耗优化研究提供支持。
- Based on the design of instruction pre-fetch FIFO for an embedded RISC processor, a SDRAM power model has been presented to optimizing the FIFO design. 本文从一个嵌入式RISC处理器的指令FIFO设计出发，提出了SDRAM的功耗模型，基于该功耗模型，提出了最优化的指令FIFO设计。
- Software pipelining is a loop optimization technique used to exploit instruction level parallelism. 摘要 软件流水是一种循环程序的优化技术，它可以有效地提高指令级并行性。
- Source level debuggers can hide execution details. Step through critical code at the instruction level. 源代码级的调试器可能隐藏运行细节。在指令层级上检查重要的代码。
- This paper presents the implementation approach and the experimental results of multimedia realtime processing on the ILP (Instruction Level Parallelism) computing platform. 论了指令级并行运算环境中多媒体数据处理的实现方法和性能。
- The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper. 本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题.
- According to the plow chain working condition,this paper constructed the power model for plow chain. 根据刨链的工作状况,建立刨链的受力模型图。
- Francis turbine is applicable for the middle and low water level power station,Both have vertical and horizontal structure,and commonly designed in the scroll. 混流式水轮机用于中、低水头电站，有卧式、立式两种，一般采用金属蜗壳。
- Since the earth leakage protection circuit of KV level power supply system was frequently out of order in Huozhou mining bureau,the reform of the circuit was done. 针对霍州矿务局千伏级供电系统漏电保护电路,经常发生故障的现象,提出对该漏电保护电路进行改造,对于改制的原理及方法都进行了较为详尽地阐述。
- The relation between Cx activity and time accorded with power model, but which between BG activity and time could be displayed S model. C_N酶活性与反应时间的关系符合幂曲线模型，BG酶活性与反应时间的关系则符合S形曲线模型。
- EPIC defines a new style of architecture that enables higher levels of instruction level parallelism (ILP) without unacceptable hardware complexity. EPIC是一种显性并行指令计算体系结构，主要思想是利用编译器和处理器的协同能力来提高指令级并行度。
- If IP vendors provide such a power model, IP users can estimation the power consumption of IPs with only input and output information under a function-level simulation. 假如矽智产供应商提供这样的功率消耗模型，则矽智产使用者只须要使用功能层级模拟得到的电路输入及输出资讯就可以推估电路之功率消耗值。
- The comparison experiments for software pipeline and super block scheduling are done, which shows that the optimization effect can be increased by more than 30% and has obvious relation to instruction level parallelism (ILP). 对编译后端的软件流水和超块调度两种性能优化策略进行对比实验;表明其优化效果在30%25以上;并且代码的指令级并行性(Instruction Level Parallelism;ILP)与优化效果存在明显的相关性.
- Aresearching focus is electric rotary tillers that can better suit the condition of the agricultural greenhouses and the power model is core technology. 适合棚室作业的电动力微耕机是最近研究的热点,指出在该研究方向的核心技术集中在电源问题上。
- The concepts of regions in the Instruction Level Parallelism(ILP) and the Explicitly Parallel Instruction Computing(EPIC)are explained. Sevral algorithms of regional scheduling are introduced. 介绍指令级并行性 (IL P)中和指令级计算 (EPIC)中区域的直观概念和这些概念的形式化工作 ,并简单介绍区域的几个调度算法 ,为并行编译中的区域调度问题提供一个系统的、形式化的论述。
- The utility of Leap function in the crown growth process with changing point is better than the usual regression methods , and the Monadic power model is the best one. 阶跃函数模型在具有变点的桉树林分树冠生长过程中的应用优于一般回归拟合模型效果，而且以 阶跃幂函数模型为最佳。
- The concepts of regions in the Instruction Level Parallelism (ILP) and the Explicitly Parallel Instruction Computing(EPIC)are explained. Sevral algorithms of regional scheduling are introduced. 介绍指令级并行性(ILP)中和指令级计算(EPIC)中区域的直观概念和这些概念的形式化工作,并简单介绍区域的几个调度算法,为并行编译中的区域调度问题提供一个系统的、形式化的论述。
- In the designing and exploitation progress of a DSP core,the instruction level simulator can be used in the emulation and debugging,and it is propitious to expedite the rate of development. 在DSP内核的设计、开发过程中,指令级模拟器可用于汇编程序仿真、调试,有利于加快芯片开发进度。
- The power source outputs uses three end constant voltage chip to carry on the constant voltage, and carries on after the high efficiency Darington tube expands flows meets the level power need. 电源输出采用三端稳压芯片进行稳压，并且利用大功率达林顿管进行扩流以满足后级功率需求。
