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- instruction cache miss rate 指令缓存缺失率
- An instruction cache miss will occur when fetching this instruction, resulting in the fetching of the modified instruction from storage. 当取这个指令时会发生指令高速缓存失败,结果就会从存储器中取得修改后的指令。
- cache miss rate 超高速缓存故障率
- If there is no instruction cache, this subroutine may be a no-op. 如果在你的目标机上，没有指令缓存，则可能不做任何操作。
- When u see mages having a lower melee miss rate. 当你看到法师的近战命中率远低于你的。
- Indicates that the request is treated as a cache miss and the page is executed. 指示将请求当作缓存未命中处理并执行该页。
- The item is evicted from the cache and the request is handled as a cache miss. 从该缓存中收回项并将请求当作缓存未命中处理。
- On SPARC and SPARCLITE only, write this subroutine to flush the instruction cache, if any, on your target machine. 只在SPARC和SPARCLITE平台上，这一功能调用用来刷新指令缓存。
- The testing result of SPEC95 indicates that the miss rate of the BTB with 256 entries is 12.7%, while the BTB with 4K entries is 7.3%. Moreover, as for their prediction accuracy of branch instruction, both of them can reach 90%. SPEC95测试结果表明：本文所设计的256项和4K项BTB的命中失效率分别为12.;7%25和7
- Instruction to invalidate the instruction cache line that will contain the modified instruction. 指令,使将要存放修改后指令的指令高速缓存行无效。
- Pipelined level one instruction cache (PIL1) has been proposed to improve instruction fetch bandwidth in high frequency processor. 摘要流水化的指令缓冲存储器通常被用于高频率处理器中，以提高取指带宽。
- It seems like some sort of cache miss effect, but that does not make sense to me given the actual memory of the system. 看上去就象是高速缓存丢失的影响,但根据系统的实际内存它不会对于我有任何意义。
- Remember, the kernel invokes the AVC and the AVC invokes the security server if there is a cache miss. 记住,如果未击中缓存,那么核心调用AVC,AVC调用安全性服务器。
- In SQL Server 2005, when there is no cache insert after a cache miss, only an SP: CacheMiss event is written to the trace. 在SQL Server 2005中,如果在缓存未命中之后没有插入缓存,则只将SP:CacheMiss事件写入跟踪。
- These actions can cause cache misses and page faults. 这些操作可能导致缓存未命中和页错误。
- Because when large page is used, TLB(translation lookaside buffer) can map much larger virtual memory area,which leads to the reduction of miss rate. 但是通常用来处理有关军事,气象,经济等方面海量计算量应用程序,频繁的切换导致了计算性能的低下。
- Consequently, users can expect to see a reduced number of events reported for multiple cache miss events that occur for a single stored procedure or function. 因此,对于为单个存储过程或函数所发生的多个缓存未命中事件,用户可以看到对这些事件所报告的事件数有所减少。
- This paper introduced a much more precise sampling method using CPU hardware performance counters (CHPC) to provide CPU data like instruction cycles, cache misses, branch prediction, and so on, and given detail scene of software status. 摘要引入了基于CPU硬件性能计数器的性能数据采集和分析方法，从软件运行时刻的细粒度参数入手分析软件运行时刻的性能表现，从而更为准确地反映系统实际的动态运行状态。
- Dual Wielding vs Two Handed WeaponsThere's arguments for both. The damage output is pretty similar overall due to the miss rate of the offhand of a dual wielder. 双手挥舞vs双手武器对两者的选择是有争议的。因为存在双持的命中惩罚,所以输出的伤害大体上是差不多的。
- We use TDT3 corpus as test corpus. The best tracker achieves 4.0% miss rate and 1.8% false alarm. The tracking cost is 0.0029 and Norm(C_(track))is 0.1239. 本文选用TDT3语料作为测试语料;系统达到最好的追踪性能时;在漏报率为4.;0%25的情况下;误报率仅为1
