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- gate level logic simulation 门级逻辑模拟
- After study a series array multipliers algorithms and architectures, . the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill. 本文研究讨论了各种不同阵列乘法器的结构和原理,并完成了在门电路级设计了32位基4Booth编码并采用42压缩的Wallace高性能阵列乘法器电路。
- The verification includes RTL simulation, gate level simulation and static timing analysis. 验证工作包括RTL级仿真、门级仿真和静态时序分析。
- This thesis has accomplished the design of register transfer level (RTL) of every unit in the digital processing module, and passed function verification, logic synthesis, and gate level verification. 本文完成了数字处理模块各个单元的寄存器传输级（RTL）设计，并通过了功能仿真、逻辑综合与门级仿真。
- Finally and some discussions are made on the advantages and disadvantages of the Gate Level Evolvable Hardware. 在函数级进化中，首先在FPGA内部设计了用高级功能模块和互连矩阵构成函数级进化的结构，探讨了如何利用这种结构缩短染色体编码并设计了用于函数级进化的系统平台。
- The design, now, has passed the logic simulation successfully in Daisy computer workstation. 目前，线路级的设计已经完成，并且成功地通过了Daisy工作站的计算机逻辑模拟。
- Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping. 高级综合结果中常量元件和输出悬空端口导致门级工艺映射结果中存在显式冗余。
- An expetr system is designed based on peculiarities of substation operation and by applying artificial intellesence theory and Principle of logic simulation. 本文根据变电运行的特点，应用人工智能和逻辑仿真的原理，给出了由模拟量和计算机系统组成的硬件系统方案。
- In order to improve the security of the system, the breakers are operated to control the power of the sluices in the dynamoelectric method and the gate level gauge is composed of absolute Gray coder and elastic equilibrium sensor. 为了提高系统的安全性 ,采用了电动操作断路器对闸门的动力电源进行控制。 闸位计采用绝对值格雷码编码器以及弹性平衡传感器组成。
- Based on the VRM,a simple RTL logic simulator was implemented for verification of the model. 基于该模型 ;还实现了一个简单的RTL逻辑模拟程序以验证VRM模型的可行性 .
- This flow could use the gated clock,the operand isolation and the gate level optimization to decrease the power consumption without changing the original design. 这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
- The latter is implemented through comparing the two different results from Ski IA-64 hardware simulator and Verilog-XL logic simulator. 后者是通过比对同一测试码在Ski IA-64硬件模拟器和Verilog-xL逻辑模拟下的不同运行结果实现的。
- gate level combinational circuits [计] 门级组合电路
- Eseutil verifies the page level and Extensible Storage Engine (ESE) level logical integrity of the database but does not verify database integrity at the Information Store level. Eseutil可验证页级别和可扩展存储引擎(ESE)级别的数据库逻辑完整性,但不会验证信息存储级别的数据库完整性。
- A man appeared at the castle gate in the guise of a woodcutter. 一个男子打扮成樵夫的模样出现在城堡的门口。
- Did you remember to padlock the gate? 你是否记得用挂锁把大门锁上？
- Design of a Platform for Logic Simulation and Testing 一种逻辑仿真测试平台的设计
- I saw him make by the gate on his bicycle. 我看见他骑自行车从大门旁边过去了。
- The truck came to a dead stop out of the gate. 那辆卡车在大门外突然停下。
- Programme of Universal Logic Simulation for Electronics 通用电子逻辑模拟程序
