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- The verification includes RTL simulation, gate level simulation and static timing analysis. 验证工作包括RTL级仿真、门级仿真和静态时序分析。
- gate level simulation 门级模拟,门电路级模拟
- gate level simulator [计] 门级模拟程序
- Finally and some discussions are made on the advantages and disadvantages of the Gate Level Evolvable Hardware. 在函数级进化中，首先在FPGA内部设计了用高级功能模块和互连矩阵构成函数级进化的结构，探讨了如何利用这种结构缩短染色体编码并设计了用于函数级进化的系统平台。
- Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping. 高级综合结果中常量元件和输出悬空端口导致门级工艺映射结果中存在显式冗余。
- After study a series array multipliers algorithms and architectures, . the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill. 本文研究讨论了各种不同阵列乘法器的结构和原理,并完成了在门电路级设计了32位基4Booth编码并采用42压缩的Wallace高性能阵列乘法器电路。
- We designed an RTL testbench for asynchronous sampling, an RTL level simulation testbench and a FPGA platform for the chrominance demodulation. 对色度处理算法设计了完整的RTL级仿真平台和FPGA硬件验证平台。
- It is proved by analysis in theory and system level simulation that the adaptive congestion control algorithm can enlarge system throughput while controlling system load. 经过理论分析和系统级仿真，验证了自适应拥塞控制算法在控制系统负载的条件下，提高了系统吞吐量。
- In order to improve the security of the system, the breakers are operated to control the power of the sluices in the dynamoelectric method and the gate level gauge is composed of absolute Gray coder and elastic equilibrium sensor. 为了提高系统的安全性 ,采用了电动操作断路器对闸门的动力电源进行控制。 闸位计采用绝对值格雷码编码器以及弹性平衡传感器组成。
- This thesis has accomplished the design of register transfer level (RTL) of every unit in the digital processing module, and passed function verification, logic synthesis, and gate level verification. 本文完成了数字处理模块各个单元的寄存器传输级（RTL）设计，并通过了功能仿真、逻辑综合与门级仿真。
- A fast simulation environment has been developed using MATLAB and SIMULINK for behavioral level simulation of spread spectrum clock generator based Fractional-N frequency synthesizers. 摘要提出了一种展频时钟生成的方法，使用MATLAB和SIMULINK开发出了快速模拟基于分数N型频率合成器的展频时钟生成器的环境。
- This flow could use the gated clock,the operand isolation and the gate level optimization to decrease the power consumption without changing the original design. 这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
- At last, the system simulation under different conditions was accomplished by inserting the obtained lumped parameter models into a system level simulator. 将这些物理参数综合在系统仿真器中与外围电路共同进行仿真，准确地评估不同条件下微机械陀螺的行为特性。
- gate level combinational circuits [计] 门级组合电路
- A man appeared at the castle gate in the guise of a woodcutter. 一个男子打扮成樵夫的模样出现在城堡的门口。
- Did you remember to padlock the gate? 你是否记得用挂锁把大门锁上？
- System Level Simulation of Pipelined ADC 流水线ADC的系统级仿真
- I saw him make by the gate on his bicycle. 我看见他骑自行车从大门旁边过去了。
- The truck came to a dead stop out of the gate. 那辆卡车在大门外突然停下。
- VHDL Level Simulation and Research of Switch Fabric 交换结构的VHDL层仿真研究
