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- The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed. 定量分析了数字式锁相倍频器输出信号的相位抖动.
- The basic principle of using phase locked loop technique to realize the design and analysis of program controlled frequency syntheses was introduced. 本文简要地叙述了应用锁相环路实现信号合成的基本原理。
- One example is the phase comparator of a phase locked loop. 一个例子是相锁环状态下的相位比较器。
- The frequency and phase lock loop has been applied for the carrier recovery of VSB transmission system in high definition TV. 目前，锁频锁相环在高清晰度电视VSB传输系统载波恢复中得到了应用。
- After the signals treated by a digital phase locked loop of zero phase-difference when phase and frequency following,this problem has satisfactorily been solved. 采用对相位和频率跟踪无相差的数字锁相环对同步信号进行处理可满意地解决上述问题。
- To meet the requirements of the target radio frequency (RF) hardware-in-the-loop simulation of the radio detonator, a method using a special phase lock loop (PLL) is presented. 摘要针对某型导弹无线电引信目标射频半实物仿真的需要，提出了一种特殊的环路锁相方法。
- To meet the requirements of the target radio frequency(RF) hardware-in-the-loop simulation of the radio detonator, a method using a special phase lock loop(PLL) is presented. 针对某型导弹无线电引信目标射频半实物仿真的需要,提出了一种特殊的环路锁相方法。
- Phase locked loop (PLL) has been widely used in communication system. 锁相环路在通信系统中得到了广泛的应用。
- Resolution of Systematic Design Trouble with PLD Interior Phase Lock Loop. 使用PLD内部锁相环解决系统设计难题。
- The normal idea to make up a digital controled oscillator (DCO)of the digital phase locked loop (DPLL)is to delete the pulses unwanted It need that the master clock frequency must be more faster than the output frepuency of the DPLL. 传统的数字锁相环 (DPLL)多采用吞脉冲的方法来实现DCO ,此方法要求工作频率远高于DPLL的输出频率。
- The phase noise in microwave receiver and the measured parameter of source frequency instability are described in this paper, and the technology of frequency-synthesizing and theory of Phase Locked Loop (PLL) are also briefly introduced. 摘要阐述了微波接收机中的相位噪声概念及本振源频率不稳定度的实际测量参数，并简要介绍了频率合成技术和锁相环路工作原理。
- The principle of voltage linear digital triggering of thyristor by EPROM is described and it is discussed to solve the frequency disturbance on digital trigger by phase locked loop . 描述了用EPROM实现晶闸管电压线性触发原理，讨论了用锁相环解决数字触发的频率扰动问题。
- Voltage controlled oscillator (VCO) and frequency divider (FD) are the main components of phase locked loop (PLL). For VCO, low phase noise can avoid the affection of Adjacent-Channel Interference. 摘要:压控振荡器与除频器是锁相迴路中，主要的电路之一。对压控振荡器而言，低相位杂讯可避免造成相邻通道的干扰。
- In order to realize the frequency and phase of output voltage synchronized with input voltage when UPS works, in the paper, a digital phase locked loop based on MCU with high precision is presented. 为了实现不问断电源(UPS)运行时输入输出电压频率和相位保持一致,本文结合锁相环的原理,利用单片机实现高精度的数字锁相环。
- The FLL features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. 在FLL 功能数字频率锁定环（ FLL ）的硬件，与数字调制器，稳定会计频率可编程多的观赏晶体频率。
- It adopts the way of PLL (Phase Locked Loop) and FLL (frequency Locked Loop).It not only satisfies the dynamic capability and tracking precision, but also can alternate according to the environment. 在载波跟踪中，采用了PLL(锁相环)与FLL (锁频环) 结合的载波跟踪方案，使得跟踪环能够同时满足动态性能与跟踪精度的要求，且根据环境的变化使PLL和FLL交替工作。
- Firstly, the principle and realization of the step acquisition and delay locked loop are discussed. 首先，论文讨论了步进捕获延迟锁定环的原理及实现机理。
- TMS320F240 DSP is used to realize the digital Phase Locked Loop(PLL) and real-ize the hot-swap function of the parallel system. 采用TMS320F240型DSP芯片实现数字锁相同步,实现并联系统的热插拔功能。
