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- Based on the design of instruction pre-fetch FIFO for an embedded RISC processor, a SDRAM power model has been presented to optimizing the FIFO design. 本文从一个嵌入式RISC处理器的指令FIFO设计出发，提出了SDRAM的功耗模型，基于该功耗模型，提出了最优化的指令FIFO设计。
- Development of the embedded RISC processor technology 嵌入式RISC处理器技术的发展现状
- embedded RISC processor 嵌入式RISC处理器
- ARM CPU is a kind of advanced 32-bit embedded RISC microprocessor. 摘要ARM处理器是目前公认的业界领先的32位嵌入式RISC微处理器。
- This paper introduces 32 bit embedded RISC microcomputer that is developed by dint of our country. 本文介绍我国自行研制的32垃嵌入式risc微计算机。
- For purpose of illustration, a RISC processor that embeds a direct-mapped data cache is employed for the experiments. 为了验证我们的测试方法，我们使用一个拥有直接映射记忆体的处理器来当我们的测试样本。
- The latest RISC processor also guarantees high throughput speed which is perfect for large graphic data. 最新的RISC处理器进一步保证了快速的打印，并能够完美打印出较大的图片信息。
- "It provides a high level design for a thorough optimizer, code generator, scheduler and register allocator for a generic modern RISC processor. 作者在编译器的实践方面经验丰富，主要关注如何选择编译技术，技术的工程实现以及如何对技术进行改进。
- The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper. 本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题.
- The AMBA bus consists of AHB/ASB(Advanced High-performance Bus) and APB(Advance Peripheral Bus). RISC processor,IP and peripheral apparatus are integrated by AMBA bus. AMBA总线由高速总线AHB/ASB(Advanced H igh-performance Bus)和低速总线APB(Advance Peripher-al Bus)2种总线机制组成,实现R ISC处理器、IP核和外设集成。
- The successful foundry of a high performance, high reliability 32-bit embedded RISC microprocessor with the first wit has proved the necessity and effectiveness of the technology for spacecraft chip. 采用了该技术的面向空间应用的高性能高可靠32位嵌入式RISC处理器取得了一次流片成功的结果。
- It's a diskless and monitorless device that comprises a RISC processor,a few MBf memory,a network interface,an input/output interface,and a system for starting up from the network. 它是一个无盘、无显示器的设备，由一个RISC处理器、几兆内存、网络接口、输入/输出接口和从网络上启动的系统组成。
- OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar32- bit RISC processors in his class and can efficiently run any modern operating system. OR1200定位于嵌入式、动和网络应用。她能够与同类的最新的32位标量处理器竞争，并且可以运行任何现代操作系统。
- Multimedia accelerator module (MMA), on-chip SRAM and the related software optimization scheme are used in our SoC, leading to a SoC design method oriented to multimedia application based on low end RISC processor core. 通过在SoC中增加多媒体加速器(MMA)模块和片上SRAM以及相关的软件优化方案,提出了一种基于低端精简指令集计算机(RISC)处理器核的面向多媒体应用(MP3)的SoC设计方法。
- It's a diskless and monitorless device that comprises a RISC processor, a few MBf memory, a network interface, an input/output interface, and a system for starting up from the network. 它是一个无盘、无显示器的设备，由一个risc处理器、几兆内存、网络接口、输入/输出接口和从网络上启动的系统组成。
- What is pipelining, anyway? It helps RISC processors run more quickly, but how? 总之，什么是流水线技术呢？它使RISC型处理器运行的更快，那么是怎么实现的呢？
- DESIGN OF A 32-BIT EMBEDDED RISC MICROPROCESSOR 32位嵌入式RISC微处理器的设计
- 32 Bit Embedded RISC Microcomputer 32位嵌入式RISC微计算机
- Network processors overcome the limitations of these two approaches by combining the programmability of RISC processors with the performance of ASICs. 网络处理器通过把RISC处理器的可编程性与ASIC的性能结合起来，克服这两种方法的局限性。
- Most RISC processors have faster floating point multiply operations than integer ones. 我见到这样一句话，你的risc处理器是啥?确定没有浮点处理吗?
