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- PLL Demodulation 锁相解调
- THE DESIGN AND PRACTICE OF THE COSTAS PLL DEMODULATOR COSTAS环解调器设计及实践初探
- Signal demodulation of automatic block with audio frequency shift modulated track circuits was implemented with phase-locked loop( PLL) technique and a singe chip microcomputer. 利用锁相环(LL)窄带跟踪特性;与单片机结合;实现自动闭塞系统移频信号解调.
- The signal processing circuses, including the low-noise pre-amplifier, the filter and the phase lock loop(PLL) demodulation were designed. 分析并研制了系统的信号调理电路，其中包括低噪声前置放大、滤波、锁相环解调。
- It offers Dolby C, a PLL servo mechanism. 它提供了对杜比C降噪的支持。
- A full digital demodulation scheme is proposed for HF QAM signal. 文中针对短波高速QAM信号,提出并实现了一种全数字的解调方案。
- Finally it is demonstrated by simulations that, once PLL is capable of retrieving tracking state from capturing state in some SNR condition, effective EBPSK demodulation is available. 分析表明，在一定的信噪比条件下，只要锁相环能由捕获状态恢复到跟踪状态，就能保证EBPSK信号的有效解调。
- This paper described the performances of capture and track of phase-lock-loop used in PLL synchronous demodulation in color TV，and pointed out the reasons which affected the performances. 分析了彩电PLL同步检波技术中锁相环路的捕获与跟踪特性，并指出了影响其特性的原因。
- The paper proposes a new method of demodulation of PCM/DPSK signal. 提出了一种新的PCM/DPSK数字信号解调方法。
- The phase noise of PLL is?88.83 dBc/Hz at 10kHz offset. 37GHz的单片锁相环电路的锁定范围为32MHz;锁定时在偏离中心频率10kHz处的相位噪声为-88.;83dBc/Hz。
- Understand clock synchronization using phase-lock loop (PLL). 理解用锁相环（PLL）实现时钟同步。
- VCO is the major contributor of the PLL output noise. 压控振荡器是锁相环噪声的主要来源。
- The nether system adopts LPC936 chip to demodulation, firing control. 下位系统采用LPC936单片机系统完成远端通信和中断点火控制。
- How will it be happened when IO port is set to output and internal PLL HIGH? 当Port7设定成输出且启动内部上拉电阻时,会发生什么情形?
- Phase locked loop (PLL) has been widely used in communication system. 锁相环路在通信系统中得到了广泛的应用。
- They produce jitter.A low jitter design is important in PLL circuit. 因此在锁相迴路电路设计中拥有低杂讯抖动是很重要的。
- The paper put forward to adopt the method that the signals were preamplified and modulated by amplitude modulation, then demodulated by AM in-phase demodulation using PLL. 本文提出采用先经前置放大、调幅调制，然后再利用锁相环构成的调幅波同步检波电路解调得到有用信号的方法解决该问题。
- Ich habe die Modulation und Demodulation des analogen und digitalen Signal gelernt. 我学了模拟和数字信号的调制与解调。
- The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed. 定量分析了数字式锁相倍频器输出信号的相位抖动.
- Demodulation: The reverse of modulation. To convert data from analog to digital form. 解调:与调制相反工作。把数从模拟量转换成数字量。
