In this thesis, a low power 12bit 80MS/s pipelined ADC is designed in TSMC 3.3V 1P5M 0.25um CMOS process.是什么意思_In this thesis, a low power 12bit 80MS/s pipelined ADC is designed in TSMC 3.3V 1P5M 0.25um CMOS process.在线翻译_英语_读音_用法_例句