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- A reusable and low power RISC CPU IP core design is proposed in this paper. 研究设计了一个可重利用、低功耗的精简指令计算机 (RISC)中央处理器的知识产权 (IntellectualProper ty)核。
- Development trend of the IP core design with reuse and microcontroller is introduced in this paper,and the present situation of design technologies for microcontroller is discussed. 介绍了IP核复用技术及微控制器的发展趋势,探讨了国内外微控制器芯片设计的现状;
- IP Core Design of Haffman Encoder Based on VHDL 基于VHDL的哈夫曼编码器的IP核设计
- IP Core Design of a Parallel Interface Controller 并行接口控制器IP核设计
- Adaptive Clock Gating Technique for Low Power IP Core Design in SoC 应用于片上系统中低功耗IP核设计的自适应门控时钟技术
- IP Core Design of RPE-LTP Speech Codec Based on FPGA 基于FPGA的RPE-LTP语音编解码的IP核设计
- Research on the Sub-Deep Micro Theory and Technology of IP Core Design 深亚微米理论及IP核设计技术的研究
- Research on Verification Method and IP Core Design of Tri-port Ethernet Interface Module and Development of IAD Specific SoC 三端口Ethernet接口IP核的设计、验证方法研究及IAD专用SoC的研制
- A new IP core for LCD drivers has been designed. 介绍一种全新LCD驱动电路IP核的总体设计。
- This paper deals mainly with how to design the USB2.0 device IP core. 文中设计了符合USB2.;0规范的USB设备控制器IP软核。
- The reuse of multimedia processor IP core is the key and difficulty of programmable media SOC design. 媒体处理器IP核重用成为可编程媒体系统芯片设计的重点和难点。
- Using TCP / IP internetworking to second, with the core design implementation, TCP / IP network programming classic essential. 用TCP/IP进行网际互联第二本，设计实现与内核，TCP/IP网络编程必备经典。
- SDU_M08 IP Core is an 8-bit RISC MCU developed by the ASIC design centre of Information and Technology school in Shandong University. 本课题所设计的SDU_M08 IP核是山东大学信息学院集成电路研究中心所设计的一款8位RISC微控制器。
- After that, the design flow of HMAC/SHA-1 IP core is elaborated with detailed functional module division and state machine diagram. 为了提高TPM对HMAC和SHA-1的使用效率,我们针对TPM的规范制定了设计目标,提出了一种HMAC/SHA-1的优化实现方案。
- In FPGA module, we apply IP core technology to realizing ATA-3 protocol. 在FPGA模块中利用IP核技术实现了ATA-3协议。
- Since systemC language was good at behavior description,design method of behavior models and testbenchs using systemC instead of HDL in IP soft core design were introduced in this paper. 以一个通用异步收发器的IP核设计为例,详细讨论整个IP软核的设计流程,重点分析了行为模块和验证模块的设计。
- In order to reuse easily ,this IP core uses the Avalon bus interface and completes the function simulation in Modelsim. 为了满足复用,该IP核采用Avalon总线接口,同时利用Modelsim进行了功能仿真。
- The IP core is made up of four modules, which are alu_module,control_ module,timer_module and port_module. 这个IP模型主要由运算器模块，控制器模块，时钟模块和端口模块四个部分组成。
- Two IP cores are used as examples of how the Pilchard design flow is to be applied. 二个IP 核心被使用作为例子的怎样沙丁鱼设计流程将被申请。
- Sothe methods can be used for the core design of reactors which contain gadolinia burnablepoison. 认为本方法可以用于含钆可燃毒物的堆芯设计。
