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- variable master clock 可变主钟
- The Processer Clock is the Master Clock. 请教高手:处理器时钟,主机时钟,外设时钟的关系?
- Screening Tests on master clock culture medium of Agrocybe aegerita(Brig.)Sing. 杨树菇母种培养基筛选试验
- The level difference of these re-sults at SO is a main reflection of the level difference of UTC master clock. So结果的水平差异主要是协调世界时主钟水平差异的反映;
- The normal idea to make up a digital controled oscillator (DCO)of the digital phase locked loop (DPLL)is to delete the pulses unwanted It need that the master clock frequency must be more faster than the output frepuency of the DPLL. 传统的数字锁相环 (DPLL)多采用吞脉冲的方法来实现DCO ,此方法要求工作频率远高于DPLL的输出频率。
- The master clock can be asynchronous with PCM data side clock or ADPCM data side clock. Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的,不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的;
- The master clock can be asynchronous with PCM data side clock or ADPCM data side clock.Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的,不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的;
- This essay mainly introduced electric time synchronous net-form mode,the basic concept and the determinant of GPS system.The basic technical need of substation GPS master clock is briefly summarized. 主要介绍了电力时间同步组网模式、GPS系统的基本概念及其决定因素,并对变电站GPS主时钟的基本技术要求作了简短小结。
- best master clock algorithm(BMC) 最佳主时钟算法
- Best Master Clock (BMC) algorithm 最佳主时钟算法
- master clock frequency of a computer 计算机主频
- A constant, variable, function name, or expression. 一种常数、变量、函数名或表达式。
- The prices are variable, shop around by all means. 价格高低不一,所以一定要货比三家逐店选购。
- The temperature was a variable in the experiment. 在该实验中温度是个变量。
- The cruel master beat his slaves with a whip. 残酷的主人鞭打他的奴隶。
- A finite increment in a variable. 变量增量变量的有限增量
- The speed of the toy boat is variable. 玩具船的速度是可变的。
- Winds are mainly light and variable. 风力较弱,风向多变。
- A great poet is a master melody. 大诗人也是音律大师。