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- Switched capacitor( SC) unit delayer, positive negative proportors and adder were designed using two phase clocks. 用二相时钟设计了对寄生电容低灵敏的开关电容单位延时器、负比例器和加法器.
- two phase clock 二相时钟
- pseudo two phase clock 准二相时钟
- Method is called, or the two phase commit methods defined in ther. 接口中定义的两阶段提交方法。
- The cure of before two phase is dialytic before cure. 前两阶段的治疗为透析前治疗。
- Trigger control circuit from complex programmable logic device (CPLD), ICL7135CN, the clock pulse circuit and optocoupler inverter constituted. 触发控制电路由复杂可编程逻辑器件(CPLD),ICL7135CN,时钟脉冲电路、反相器和光耦构成。
- In chapter two, a three nonoverlapping phases clock generator is presented at first and the experimental results are given finally. 在第二章中,一各三相非重叠电路将会被提出,而其实验结果将会被论述在本章之末。
- The transaction manager can still send two phase commit notifications instead. 事务管理器仍然可以发送两阶段提交通知。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时,(或者在最后一个时钟脉冲的下降沿之后)主机将时钟拉低,键盘/鼠标不必重新传输任何数据。
- ADD: WenLing City NanQuan two phases industry area. 地址:温岭市南泉二期工业区。
- The period falls into two phases. 这个时期又可分为两段。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/ mouse does not need to retransmit any data. 如果在第一个高->时钟跳变时,(者在最后一个时钟脉冲的下降沿之后)机将时钟拉低,键盘/标不必重新传输任何数据。
- This period of history falls into two phases. 这一段历史分为两个阶段。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the a last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时,(或者在最后一个时钟脉冲的下降沿之后)主机将时钟拉低,键盘/鼠标不必重新传输任何数据。
- Master PK warrior in two phases to resolve! 法师PK武士分两个阶段来解析!
- The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register. 触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟),这取决于移位寄存器的设计。
- Note that a set of lights attached to O1, O2, O3 would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse. 注意,一组接在O1,O2,O3上的灯泡将以二进制(模8)形式显示第一个脉冲以来已完成的完整时钟脉冲数。
- two phase closed loop pulse system 二相闭路脉冲系统
- The HKMC's business is being developed in two phases. 按揭证券公司的业务分两个阶段发展。
- A microprocessor designer may decide to make all instructions last five clock pulses. 微处理机设计人员可以决定使所有的指令持续五个时钟脉冲。