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- This change of capacitance value can be detected by TS. TS可以探测到电容量的这种变化。
- Are there any precautions when adjusting the capacitance value? 调整电容值时有哪些注意事项?
- One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells. 有覆盖金属层或阱区时,须考虑寄生电容。
- Measure capacitance value in Farad unit by RC time constant operation. 用RC时间持续运转来测量法拉单位的电容值。
- One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance. 避免金属在多晶硅栅上走线,会增加寄生电容。
- Can you ship Trimmer Capacitors with the angle and capacitance value preset? 你们可以提供带预设角和电容值的微调电容器吗?
- It details the IC design process and VLSI circuits, including gate arrays, programmable logic devices and arrays, parasitic capacitance, and transmission line delays. 它详细规定了集成电路设计过程和超大规模集成电路电路，包括门阵列，可编程逻辑器件和阵列，寄生电容，及输电线路的延误。
- The various applications and features are described of gate-source parasitic capacitance with synchronous rectifier diodes in the realization of actuating rectifier. 阐述了同步整流管的栅源寄生电容在实现整流器件驱动中的不同应用及其特点,并给出了应用实例分析。
- First, the capacitor inserted allows a low frequency "extension" due to the resonance between the transformers inductance and the capacitance value. 第一，耦合电容和变压器初级电感之间的谐振可以容许更好的低频延展。
- Which Trimmer Capacitors have small minimum capacitance values? 哪种微调电容器有最小电容值?
- Likewise , C1 must have a large capacitance value is order to provide operating current for the load when D1 and D2 are not conducting. 同样，C1容量必须足够大，才可以保证在D1和D2不导通期间为负载提供运行电流。如果C1容量太小。
- Due to the introduced PN junction, the photocurrent is made up by both electronic and pole.As a result, the sensitivity and signal to noise ratio are increased, the parasitic capacitance is decreased. 由于引入PN注入结，新型光电器件沟道电流同时存在电子电流和空穴电流，提高了器件的响应灵敏度，避免了大的寄生电容，提高了信噪比。
- A novel configuration of a MOS varactor is designed for good linearity of Kvco,as well as a new digital capacitor controlled array topology with lower parasitic capacitance and lower Ron. 通过改变MOS变容管的接入方法实现了更好的压控增益线性度,并采用了新的低寄生电容、低导通电阻的数控电容阵列结构来补偿工艺变化带来的频率变化。
- Silicon on insulator(SOI) structure, as a very large scale integrated circuit(VLSI) wafer, has attractive features such as radiation-hardening, no parasitic capacitance and latch-up effect. 绝缘体上生长的薄单晶硅膜(SOI)具有良好的横向绝缘、抗辐照、无锁存效应和无寄生电容，并能有效地提高硅集成电路的速度和集成度，在深亚微米VLSI技术中，具有很大的优势和潜力。
- The impacts of these parasitic capacitances on interface circuit are analyzed. 建立了某种硅微机械陀螺仪的电路模型,分析了寄生电容对接口电路的影响。
- In the measurement process, the 66 capacitance values from ECT sensor are the input of the voidage model, and the output of the model is the voidage value. 运用该方法测量空隙率时，以ECT电容传感器获取的66个独立电容值作为空隙率模型的输入，计算即可得空隙率。
- The parasitic capacitances of IGBT and other distributed parameters would induce adverse effects to drive wave. 栅极驱动电压必须有足够快的上升和下降速度。
- controllable parasitic capacitance 可控寄生电容
- At last,some methods,such as the adoption of SOI craftwork and reasonable disposal wires,are put forward to decrease the parasitic capacitances. 提出了采用新工艺和合理的布线方法减小与活动结构间的电容，从而提高信噪比。
- In previous work a noncirculating type of bearing current caused by parasitic capacitive coupling from stator windings to the rotor was identified. 在早先的工作中一非循环类型生由从固定子卷到转子的寄生电容的联结所引起的涌流被识别。
