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- memory bus interface 存储器总线接口
- There are five parts in PowerPc603e? microprocessor: Integer Execution Unit, Floating Point Unit(FPU), Instruction(Data) Cache, Bus Interface Unit and Memory Manage Unit. PowerPc603e微处理器系统由定点执行单元、浮点单元、指令(数据)Cache、总线接口单元、存储管理单元组成，以流水和超标量方式执行指令。
- With SMP, all memory access is posted to the same shared memory bus. 通过SMP,所有的内存访问都传递到相同的共享内存总线。
- Functionality in this area includes bus interface circuitry and a level2 cache. 本区域的功能包括总线接口线路和二级缓存。
- There are five parts in VEGA microprocessor, which hires five-stage pipeline: Integer Execution Unit (IEU), Memory Subsystem Unit (MSU), Registers, Pipeline Control Unit (PCU) and Bus Interface Unit (BIU). VEGA处理器由定点执行单元、储存子系统(MMU、I-Cache和D-Cache)、寄存器堆、流水线控制单元和总线接口单元BIU五部分组成,采用五级流水线执行指令。
- The external memory bus may be isolated from MCU and the bus is released to the DMA controller. 外部资料汇流排可以与微控制器隔离开来，好释放给DMA控制器使用。
- This paper introduce the I2C bus interface of S3C44B0X, and connective method with EEPROM. 文章介绍了S3C44B0X的I2C总线接口,与EEPROM的连接方法。
- The core and the memory bus will run faster and faster, it seems more PWR/GND need to supply enough peak current. 内核与存储器总线运行速度越来越快，似乎更多的PWR/GND需要供应足够的峰值电流。
- In order to reuse easily ,this IP core uses the Avalon bus interface and completes the function simulation in Modelsim. 为了满足复用,该IP核采用Avalon总线接口,同时利用Modelsim进行了功能仿真。
- Functionality in this area includes bus interface circuitry and a level 2 cache. 本区域的功能包括总线接口线路和二级缓存。
- Details of the USB bus interface for program development of the principles, processes and routines. 详细介绍了对USB总线接口进行程序开发的原理、过程和例程。
- The adpter is composed of a bus interface module,a logic control module,an encoder/decoder and a transceiver module. 红外无线串行通信适配卡有四个模块：总线接口模块，逻辑控制模块，调制解调模块，发射接收模块。
- NUMA alleviates these bottlenecks by limiting the number of CPUs on any one memory bus and connecting the various nodes by means of a high speed interconnection. NUMA通过限制任何一条内存总线上的CPU数量并依靠高速互连来连接各个节点,从而缓解了这些瓶颈状况。
- Due to no SPI serial bus interface in MCS51 scm, MCS51 scm couldn't use SPI bus interface apparatuses. 摘要MCS51系列单片机由于不带SPI串行总线接口而限制了其在SPI总线接口器件的使用。
- This works fine for a relatively small number of CPUs, but not when you have dozens, even hundreds, of CPUs competing for access to the shared memory bus. 这种方式非常适用于CPU数量相对较少的情况,但不适用于具有几十个甚至几百个CPU的情况,因为这些CPU会相互竞争对共享内存总线的访问。
- Abstract: The logic analysis and circuit design of VME bus interface logic is introduced in the paper. 摘 要： 本文介绍了VME总线接口逻辑芯片的逻辑分析和电路设计。
- Physical shared memory bus, message translating LAN and copy shared memory network are the main interconnecting technology using in distributed real-time simulation. 分布式仿真系统可采用的联接方式主要有物理共享内存总线、消息传递网络和复制共享内存网络三种。
- Cipher Card is a hardware module based on bus interface of computer and offering cryptogram service function. 加密卡是基于计算机总线接口的、提供密码服务功能的硬件模块。
- CPU might therefore be unable to issue memory operations at peak speeds since it has to compete with the device in order to obtain access to the memory bus. 因为它必须为了要获得对记忆体汇流排的存取,以装置竞争，一个中央处理器可能因此不能够以尖峰速度发行记忆体运算。
- Freescale s S12 MCUs PPT, introduced the working mode, resource mapping, bus interface. 飞思卡尔S12系列单片机PPT，介绍工作模式、资源映射、总线接口。
