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- By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3.3. 通过小心选择这个电阻和积分电阻之间的比值（在推荐线路里，大约是数十欧姆），比较器的延迟就可能被补偿，最大的时钟频率可近似延伸到3.;3倍。
- maximum clock frequency 最大时钟频率
- The sampling clock frequency error can cause ICI. 采样时钟频率偏差将导致ICI。
- maximum clock frequence 最大时钟频率
- The Samsung S3C44BOX CPU is 32/16 bit RISC Microprocessor and uses ARM7TDMI core. Its maximum CPU clock frequency is 75Mhz. The S3C44BOX is used in fields of cheap price handle devices and industry applications. Samsung S3C44BOX是32/16位RISC微处理器，它使用ARM7TDMI内核，最高频率可达75MHZ，主要用于廉价手持设备和一般工业应用领域。
- Speed boost: The doubled CPU clock frequency results in even faster reaction of the system. 速度提升:随着CPU时钟频率的加倍,系统反应速度也比以往更快。
- For a fixed clock frequency, the extra count or counts caused by comparator delay will be constant and can be subtracted out digitally. 对于一个固定的时钟频率，由比较器延迟所引起的额外的一个计数或一些计数将是常数，而且该数字可以被减去。
- The clock frequency is 1 MHz.The device samples sensor-read data during the write operation. 时钟频率为1兆赫.;在写操作的过程中，设备从传感器独处的数据总取样。
- SOC (System-on-chip) is one kind of large scale and complex IC driven by high clock frequency. 摘要超深亚微米系统芯片具有规模大，复杂度高，系统时钟频率快的特点。
- The high clock frequency requirements will have to be weighed against the need for tighter design criteria that ensure high noise immunity. 高时钟频率的要求比高抗扰度的要求更为重要，因为高抗扰度可通过精心设计予以保证。
- First, there's the panel itself, which houses an array of pixels arranged for strobing by row and column, referenced to the pixel clock frequency. 首先，考虑平板本身，需要根据像素时钟频率，对像素阵列的行和列加载脉冲。
- This kind of technology inmicroprocessor unusual remarkableness, uses for to help the promotionnowadays the processor clock frequency. 这种技术在微处理器中非常的显著，用来帮助提升现今处理器的时钟频率。
- For example, if the slave is running at a clock frequency of 8MHz, the JTAG clock at TCK cannot run any faster than 1MHz. 对于到达和输出数据，最先传送最低有效位。
- In high speed data collection system, sometimes the sampling speed of A/D doesn't adapt to the working clock frequency of DSP. 摘要在DSP高速数据采集系统中，DSP往往不能适应A/D芯片的工作速率。
- Clock 12M for 8031, up 32 Interface, a high clock frequency and rich I/O. circuit function for a very favorable conditions. 8031的时钟为12M，I/O口可达32个，高的时钟频率和丰富的I/O，都为实现电路功能提供了非常有利的条件。
- Modern CMOS techniques can not only integrate many digital circuits into a system, but also raise the operating clock frequency of the digital systems. 摘要:随著CMOS制程技术进步，使得更多数位电路整合在一系统中，同时也提升这些数位电路的操作速度。
- This article mainly addresses the maintenance period of clock frequency of SPC exchanges in China's telecommunication network. 本文主要讨论我国电信网中程控交换局时钟频率维护周期的确定问题。
- Based on SMIC 0.18um CMOS technology, 400MHz clock frequency is achieved and the data throughput rate is 51.2 Gbps with the area cost of 164 K-gates. 基于SIMC 0.;18um标准CMOS工艺进行综合，AES IP核的规模为164Kgates，最高时钟可达400Mhz，吞吐率可达到51
- This driving method was notarized in experiment; it used 458 logic elements in 1K30 and can achieve the fastest clock frequency 25.71 MHz when 1K30-3 is used. 经实验确认;该IP核占用1K30中的458个LE;在1K30-3芯片中;最高时钟频率为25.;71MHz;能够完成液晶显示时序及控制方面的要求且控制灵活;
- The results shows that by means of the scheme discussed above,the whole system can work stably at 90MHz clock frequency and realize a dada transmission rate up to 2.88Gbps. 结果表明,利用上述设计方案可以使整个系统在90MHz的时钟频率下稳定工作,实现高达2·88Gbps的数据传输速率。
