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- multiphase clock pulse generator 多相时钟脉冲发生器
- The Processer Clock is the Master Clock. 请教高手：处理器时钟，主机时钟，外设时钟的关系？
- clock pulse generator 同步脉冲发生器
- digital clock pulse generator 数字钟脉冲发生器
- Screening Tests on master clock culture medium of Agrocybe aegerita(Brig.)Sing. 杨树菇母种培养基筛选试验
- The level difference of these re-sults at SO is a main reflection of the level difference of UTC master clock. So结果的水平差异主要是协调世界时主钟水平差异的反映；
- Trigger control circuit from complex programmable logic device (CPLD), ICL7135CN, the clock pulse circuit and optocoupler inverter constituted. 触发控制电路由复杂可编程逻辑器件（CPLD）,ICL7135CN,时钟脉冲电路、反相器和光耦构成。
- That the antenna is excited by the high? voltage bipolar pulse generator is described. 此天线由高压双极性脉冲发生器激励。
- A high voltage nanosecond pulse generator for calibrating voltage dividers with fast time response was constructed. 研制了一台高电压毫微秒脉冲发生器,它将用于标定快响应的分压器。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时，（或者在最后一个时钟脉冲的下降沿之后）主机将时钟拉低，键盘/鼠标不必重新传输任何数据。
- The normal idea to make up a digital controled oscillator (DCO)of the digital phase locked loop (DPLL)is to delete the pulses unwanted It need that the master clock frequency must be more faster than the output frepuency of the DPLL. 传统的数字锁相环 (DPLL)多采用吞脉冲的方法来实现DCO ,此方法要求工作频率远高于DPLL的输出频率。
- Multi function remote manual pulse generator for control of all axes, including 4th and 5th if ordered. 多功能遥控手动脉冲器控制所有轴，如需要可包括第4轴和第5轴。
- The master clock can be asynchronous with PCM data side clock or ADPCM data side clock. Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的；
- At the same time there also can be used to measure pulse circuit or pulse modulator for the pulse generator. 同时还出现了可用来测量脉冲电路或用作脉冲调制器的脉冲。
- The master clock can be asynchronous with PCM data side clock or ADPCM data side clock.Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的；
- The transistor pulse generator power supply is now commonly employed as a UEDM power supplier. 晶体管脉冲发生器电源共同地现在被使用如同UEDM 力量供应商。
- A Research of Temporal Behaviour for a New High-Efficiency Photoconductive Switch Pulse Generator[J]. 引用该论文 石顺祥;鲍吉龙;王永昌;杨德顺;詹玉书;赵伟;杨鸿儒;杨斌洲;张小秋.
- This essay mainly introduced electric time synchronous net-form mode,the basic concept and the determinant of GPS system.The basic technical need of substation GPS master clock is briefly summarized. 主要介绍了电力时间同步组网模式、GPS系统的基本概念及其决定因素,并对变电站GPS主时钟的基本技术要求作了简短小结。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/ mouse does not need to retransmit any data. 如果在第一个高->时钟跳变时，（者在最后一个时钟脉冲的下降沿之后）机将时钟拉低，键盘/标不必重新传输任何数据。
