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- The normal idea to make up a digital controled oscillator (DCO)of the digital phase locked loop (DPLL)is to delete the pulses unwanted It need that the master clock frequency must be more faster than the output frepuency of the DPLL. 传统的数字锁相环 (DPLL)多采用吞脉冲的方法来实现DCO ,此方法要求工作频率远高于DPLL的输出频率。
- master clock frequency of a computer 计算机主频
- master clock frequency 主时钟频率
- The Processer Clock is the Master Clock. 请教高手：处理器时钟，主机时钟，外设时钟的关系？
- The sampling clock frequency error can cause ICI. 采样时钟频率偏差将导致ICI。
- Screening Tests on master clock culture medium of Agrocybe aegerita(Brig.)Sing. 杨树菇母种培养基筛选试验
- The level difference of these re-sults at SO is a main reflection of the level difference of UTC master clock. So结果的水平差异主要是协调世界时主钟水平差异的反映；
- Speed boost: The doubled CPU clock frequency results in even faster reaction of the system. 速度提升:随着CPU时钟频率的加倍,系统反应速度也比以往更快。
- For a fixed clock frequency, the extra count or counts caused by comparator delay will be constant and can be subtracted out digitally. 对于一个固定的时钟频率，由比较器延迟所引起的额外的一个计数或一些计数将是常数，而且该数字可以被减去。
- The clock frequency is 1 MHz.The device samples sensor-read data during the write operation. 时钟频率为1兆赫.;在写操作的过程中，设备从传感器独处的数据总取样。
- SOC (System-on-chip) is one kind of large scale and complex IC driven by high clock frequency. 摘要超深亚微米系统芯片具有规模大，复杂度高，系统时钟频率快的特点。
- The high clock frequency requirements will have to be weighed against the need for tighter design criteria that ensure high noise immunity. 高时钟频率的要求比高抗扰度的要求更为重要，因为高抗扰度可通过精心设计予以保证。
- First, there's the panel itself, which houses an array of pixels arranged for strobing by row and column, referenced to the pixel clock frequency. 首先，考虑平板本身，需要根据像素时钟频率，对像素阵列的行和列加载脉冲。
- This kind of technology inmicroprocessor unusual remarkableness, uses for to help the promotionnowadays the processor clock frequency. 这种技术在微处理器中非常的显著，用来帮助提升现今处理器的时钟频率。
- The master clock can be asynchronous with PCM data side clock or ADPCM data side clock. Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的；
- For example, if the slave is running at a clock frequency of 8MHz, the JTAG clock at TCK cannot run any faster than 1MHz. 对于到达和输出数据，最先传送最低有效位。
- The master clock can be asynchronous with PCM data side clock or ADPCM data side clock.Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的；
- In high speed data collection system, sometimes the sampling speed of A/D doesn't adapt to the working clock frequency of DSP. 摘要在DSP高速数据采集系统中，DSP往往不能适应A/D芯片的工作速率。
- This essay mainly introduced electric time synchronous net-form mode,the basic concept and the determinant of GPS system.The basic technical need of substation GPS master clock is briefly summarized. 主要介绍了电力时间同步组网模式、GPS系统的基本概念及其决定因素,并对变电站GPS主时钟的基本技术要求作了简短小结。
