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- mass memory controller 大容量存储器控制器
- Using FPGA to Implement DDR Memory Controller Scien? 利用FPGA实现DDR存储器控制器
- The functions of system design of MP3 carried in the car are to play the MP3 audio document on the USB mass memory device and to receive FM stereo. 车载MP3的系统设计具有播放USB海量存储设备上的MP3音频文件及FM立体声收音功能。
- According to Blenheim Stalk in Muggles Who Notice, some Muggles "escape" Mass Memory Charms on occasion that are used to cover up major incidents (FB). 当魔法部致力于不让麻瓜知道魔法世界的工作时,这些通常被作为最常用的咒语。
- The memory controller offers dedicated locks to limit access to SMRAM memory only to system firmware (BIOS). 内存控制器提供独用的锁定机制,来限制只有系统固件(BIOS)能访问SMRAM。
- The DMMU consists of address translation unit (ATU) and double data rate (DDR) memory controller. 分散式记忆体管理单元包含位址转换单元和双倍资料率记忆体控制器。
- A prefetching policy in memory control system is proposed, which uses the idea of stream buffer proposed by Jouppi. 结合目前龙芯2号处理器系统总线的相关特征,提出了一种在存储控制系统内部实现的写缓存技术以提高系统的有效访存带宽。
- The target of DFI standard is a kind of between logic of definition memory controller and PHY interface general interface. DFI规范的方针是界说存储节制器逻辑和PHY接口之间的一种通用接口。
- The main computer was connected with PMAC via DLL of PCOMM. Using multimedia timer and multithreading technologies,real-time gathering data,mass memory,data upload and display function,and so on have been realized. 通过PCOMM这个动态链接库建立上位机同PMAC之间的连接;采用多媒体定时器技术与多线程技术;解决了实时数据采集、海量存储、数据上载及显示功能.
- A demo system with the name, uCRISC, is designed based on SRISC. The system consists of SRISC processor, Wishbone bus, memory controller, and otherperipherals. 设计了基于SRISC的演示系统uCRISC,该系统包括S班SC微处理器、Wishbone总线、内存控制器以及计时器、中断控制器等外设;
- According to the timing characteristics of SDRAM, the design makes use of a VHDL state machine,with focus on the implementation of techniques of multi-port memory controller. 根据SDRAM器件的控制时序特点,采用VHDL状态机的设计方法实现了多端口存储控制器的技术。
- It uses a 90 nanometer traces, and includes 128KB L1 cache + 256KB L2 cache and its own memory controller for DDR SDRAM, with a "hyper-transport link" of up to 800 MHz. 它采用90纳米的痕迹,其中包括128KB的一级缓存+ 256KB的L2高速缓存和自己的内存控制器为DDR SDRAM内存,以“超运输联系”的高达800兆赫。
- In these plan, memory controller by compositive to NAND memory chip or to it side by side, offerred for lead plane system thereby more standard interface. 在这些方案中,存储节制器被集成到NAND存储芯片或者与之并排,从而为主机系统供给了更尺度的接口。
- A cloud is a mass of vapor in the sky. 云是天空中的水汽团。
- The terrible scene was engraved on his memory. 那可怕的情景铭记在他的记忆里。
- The mass rally was a total fiasco. 那次群众集会彻底失败。
- Normally, physical addresses corresponding to the location of SMRAM would be un-cacheable and any write accesses to these addresses would be dropped by the memory controller (chipset). 一般来说,对应于SMRAM位置的物理地址是不可缓存的,这样任何对这些地址所进行的写操作将被内存控制器(芯片组)忽略。
- Let's collect the sap before its consolidation into a hard mass. 让我们在树液坚固成团之前将之收集起来。
- The technology is very useful in designing ASIC's and SOC's,where embedded memory controllers are needed. 这种设计方法可广泛应用于ASIC芯片、SOC系统等需要嵌入存储控制器的场合。