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- Flash memory at the maximum 72 MHz system clock rate. 最大能到系统时钟的速度，不过前提是顺序指令结构。
- Keyword: FPGA, PCI, Logic Analyzer, Cipher Coprocessor, Experimental system. 关键词：FPGA;PCI;逻辑分析仪;密码协处理器;实验系统
- One 1995 microprocessor uses this deeper pipeline to achieve a 300-megahertz clock rate. 一台1995年生产的微处理器用这种更先进的流水线操作可达到300兆赫的时钟频率。
- How Much Bandwidth does the Logic Analyzers need? 逻辑分析仪需要多少带宽?
- The number of stages completed each second is given by the so-called clock rate. 每秒所完成的步骤数目用所谓的时钟频率来表示。
- This paper discusses the design of VISA-based VXI bus logic analyzer module under Labwindows/CVI. 本文介绍了在Labwindows/CVI环境下基于VISA的VXI总线逻辑分析仪模块驱动程序的设计。
- In particular, they used a molecular clock rate derived from invertebrates, which is slower than the one based on vertebrates. 特别的是，他们使用从无脊椎动物推衍出的分子时钟，速度比脊椎动物的分子时钟要快得多。
- It contained the infrared logic analyzer on position machine to accept the procedure and the lower position machine procedure. 详细说明:它包含了红外线逻辑分析仪的上位机接受程序和下位机程序。
- Set clock rate if a DCE cable is connected. Skip this step if a DTE cable is connected. 假如是DCE缆线连接的话，设定时钟速率。假如是DTE缆线连接的话，跳过此步骤。
- Based on the analysis above, this paper brings out the design and implement of the embedded simulation testing tool, software logic analyzer, SimLA. 在上述研究的基础上,设计并实现了一种嵌入式仿真测试工具-软件逻辑分析仪SimLA。
- When a processor operates with a CPU clock rate of 100 MHz it can support a maximum of 25M 16-bit transfers per second. 当CPU时钟频率为100MHz时,DMA单通道能达到的16位最高传输率为25M/s。
- A principle of a embedded logic analyzer based on FPGA was introduced in this paper. and result of simulation of the part control circuit is gaven. 摘要介绍了一种基于FPGA的嵌入式逻辑分析仪的工作原理，给出了它的部分控制信号的仿真结果。
- It can properly satisfy the needs of practice of IC design, embed operating system as well as Logic Analyzer and Cipher Coprocessor. 可作为逻辑分析仪、密码协处理器使用，也可用于信息安全、IC设计、嵌入式操作系统等有关的研究、开发和实验。
- The new protocol used open collector signalling to allow multiple cards on the same bus but this actually causes problems at higher clock rate. 新协议可支持多种卡在同一总线上工作,但这也引起了一些问题。
- JTAG protocol analysis software, with Zhou meritorious LA1032 logic analyzer use, can observe various JTAG Emulator for the communication process. JTAG协议分析软件;配合周立功的LA1032逻辑分析仪使用;可以观察各种JTAG仿真器的通信过程.
- This entry specifies the maximum offset, in seconds, for which W32Time tries to adjust the computer clock by using the clock rate. 该项指定W32Time尝试使用时钟速率调整计算机时钟的最大偏移量(以秒为单位)。
- Thus, we hypothesized that as Windows XP senses that the CPU is idle, it triggers or allows the CPU to step down its clock rate. 因此,我们猜测当Windows XP判断CPU处于空闲状态时,它就触发或者允许CPU降低其时钟速率。
- The analyzer shows us in the form of haddock, and displays through PC.It can not only integrate with other tasks as part of design, but can also be used as Logic Analyzer. 该逻辑分析仪以黑匣子的形式实现,通过PC机显示,它既可以和设计任务集成在一起,作为设计的一部分,对被测信号的时序逻辑进行分析和测试,也可以单独作为简易逻辑分析仪使用。
- You have a TestKing router that is connected to a frame relay WAN link using a serial DTE interface. What determines the interface clock rate? 你的路由器通过一个DTE串口连接到一个帧中继链路，谁提供了接口时钟呢？
- We can expect pipelines having even more stages and higher clock rates. 我们期待微处理器流水线操作，有更多的步骤和更高的时钟频率。
