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- A Statistics-Based Cache Leakage Power Estimation Model 一种基于统计信息的Cache漏流功耗估算模型
- Study on leakage power estimation and reduction methodology of CMOS circuit CMOS电路泄漏功耗估算与降低方法研究
- leakage power estimation 泄漏功耗估算
- Power gating is effective for reducing leakage power. 电源闸设计是一个让漏电流减少很有效的方法。
- Consequently, the identification and modeling of different leakage components an very important for estimation and reduction of leakage power, especially for low power applications. 因此，分析和建模漏电流的各种不同组成部分对降低漏电流功耗非常重要，特别是在低功耗应用中。
- Power estimation and optimization at high level is the key technology in SOC design. 在高层次对系统进行功耗估算和功耗优化是SOC设计的关键技术。
- Power estimation is the first step towards implementing low-power design in VLSI systems. 功耗评估是进行低功耗研究的基础。
- Experimental results show that the leakage power consumption is underestimated by 52% if thermal effects are omitted. 实验结果表明如果忽略热效应，泄漏功耗将会被低估最高达52%25。
- The simulation results show a significant improvement in stability and leakage power reduction for most circuitries. 模拟结果显示，本设计对于电路的稳定性有显著的提升，而对于漏电流也得到有效的钳制。
- Multi-Threshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption. 多重临界电压互补金属氧化物导体是解决漏电流一个很有效的技术。
- What is more,this power model can also be utilized as a testing platform for system level and software level power estimation research. 同时,此功耗评估模型也可以作为高层功耗优化研究的测试平台,为系统级、软件级功耗优化研究提供支持。
- This paper explores nanometer scale CMOS circuits leakage mechanisms and device and circuit techniques to reduce leakage power consumption. 本文分析了纳米级CMOS电路的各种漏电流组成机制并提出了相应的降低技术。
- Multivalued logic method for power estimation in VLSI[C]//Proceedings of the 14th Chinese Institute of Electronics Symposium on Circuits and Systems.Xiamen:1998:70-77. VLSI功耗估计中的多值逻辑方法[C]//中国电子学会电路与系统学会第十四届年会论文集.;厦门:1998:70-77
- The power macromodel presented in this paper is built on the word level statistics of input stream, which can be applied to the power estimation of various Audio/Video DSP chips. 文中提出的功耗宏模型建立在字级信号统计的基础上,可用于各种音/视频信号处理芯片的功耗估计。
- The experimental results on some IP cores in a real SoC show an average of 62.2% dynamic power reduction and 70.9% leakage power reduction without performance degradation. 对一款真实SoC中浮点IP核的改造实验表明;在不降低性能的前提下;可以平均降低62.;2%25的动态功耗;同时理论上平均降低70
- The cross power estimates from this averaging are refered to as a block. 由这个平均值估算的功率谱就是所提及的一个块。
- To reduce power leakage of deep sub-micron metal-oxide-semiconductor(CMOS) circuit in standby mode and search the minimum leakage vector(MLV) producing minimum leakage power,a linear programming(LP) model based on leakage power library was proposed. 为了减小深亚微米互补金属氧化物半导体(CMOS)电路待机模式下的泄漏功耗;须寻找使电路泄漏功耗最低的最小泄漏向量(MLV).
- Post simulation shows the PA exhibited a power-added efficiency of 44.8%,a gain of 27.4 dB,and an adjacent channel leakage power ratio at a 1.25-MHz offset frequency of-47.9 dBc at a out of 28 dBm with 1.228 8-Mcps HPSK modulation. 考虑了寄生效应的后仿真结果表明;该功率放大器在1 850MHz;码片速率为1.;228 8Mcps的混合移相键控调制信号的激励下;在CDMA2000系统要求的最大输出功率28dBm处PAE达到44
- Xiaotao Chang, Dongrui Fan, Yinhe Han, Zhimin Zhang. "Fast Algorithm for Leakage Power Reduction by Input Vector Control". The 6th IEEE International Conference on ASIC (Asicon2005) , October 24-27, 2005, Shanghai, China. 常晓涛，范东睿等，“应用输入向量控制技术降低漏电功耗的快速算法”，计算机研究与发展，2006年43卷5期，（946-952）。
- AdjacentChannel Leakage power Ratio (ACLR) : The ratio ofthe average power centered on the assigned channelfrequency to the average power centered on an adjacent channel frequency. 邻信道泄露功率比（ACLR）：指配信道的平均功率与相邻信道的平均功率之比。
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