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- Fabrication and Investigation of High K Gate Dielectric Materials for Next Generation MOSFET Applications 应用于下一代MOSFET中的高介电栅介质材料的研究
- high k gate dielectric 高介电常数栅介质
- Keywords SiGe;Silicon-On-Insulator (SOI);SiGe-On-Insulator(SGOI);stained Si;high K gate dielectric;plasma immersion ion implantation &deposition (PIII&D);self heating effect; 绝缘体上的硅(SOI);绝缘体上的锗硅(SGOI);应变硅;高K栅介质;等离子浸没式离子注入;自加热效应;
- For continued technology scaling, high k materials are required to replace SiO_2 as gate dielectric in the next generation metal oxide field effect transistors (MOSFET). 在过去二十多年里,Si基元器件的大小遵循Moore定律按比例的持续减小。 对于下一代金属氧化物半导体场效应管(MOSFET)器件,原来的栅极介电材料SiO_2已经不再适合使用。
- high k gate dielectrics 高k栅介质
- Keywords High k materials;Gate dielectric;Molecular beam epitaxy;HfO_2;Er_2O_3; 高k材料;栅介质;分子束外延;二氧化铪;三氧化二饵;
- NTBI induced device degradation can be suppressed by a SiN capping layer between Poly-Si gate and high k dielectric layer. 在闸极与高介电常数介电层间使用氮化矽可有效抑制负偏压温度不稳定性的现象。
- High k dielectric HfO 2 films were deposited on p type Si(100) substrates by e beam evaporation. 使用高真空电子束蒸发在p型Si(1 0 0 )衬底上制备了高kHfO2 薄膜 .
- The equivalent oxide thickness (EOT) of an HfO_2 high k dielectric is extracted in two steps. 分两步提取了HfO2高k栅介质等效氧化层厚度(EOT).
- high - k gate dielectrics 高k介质
- Second,an approach using flat-band capacitance is demonstrated for extracting the EOT of a high k dielectric,without the effects of inversion or accumulation capacitance. 其次;给出了一种利用平带电容提取高k介质EOT的方法;该方法能克服量子效应所产生的反型层或积累层电容的影响.
- Intel's new design uses what is known as high K metal gate technology. But IBM made a similar announcement on the same day as Intel. 英特尔的新设计使用的是大家所知道的“高K金属门”技术。但是,IBM公司也在同一天作了类似的宣布。
- Results show that HfO 2 gate dielectric hold good electrical characteristics. 实验结果显示 :Hf O2 栅介质电容具有良好的 C-V特性 ,较低的漏电流和较高的击穿电压。
- Ultra-thin Si 3N 4/SiO 2(N/O) stack gate dielectric with EOT of 2.1nm is fabricated successfully,and its characteristics are investigated. 成功制备了EOT(equivalentoxidethickness)为 2 1nm的Si3 N4/SiO2 (N/O)stack栅介质 ;并对其性质进行了研究 .
- Especially, the quality of gate dielectric layer determines the reliability and electrical performance of ultra large scale integrated (ULSI) circuit. 特别是闸极介电层的品质能决定ULSI电路的稳定度与电特性表现。
- We focus on how the processes in repaid thermal processor (RTP) affect the electrical characteristics quality of gate dielectric layer. 我们将会集中以快速热制程如何影响介电层电特性。
- The reliability of strain silicon,gate dielectric and copper interconnection are discussed,and some new researches are presented. 简介了应变硅材料、栅介质的工艺及铜互连的可靠性,并对新的研究方向做了介绍。
- A high K ratio method for fatigue precracking in welding position toughness specimen of thick steel plate was developed. 提出了预制厚钢板焊缝断裂韧度试样疲劳裂纹的“高K比法”。
- VoL-canic rocks and subvolcanic rocks related with metallogenesis are characteristic of rich Si,poor Fe,high K and low Na. 与成矿有关的火山岩、次火山岩具有富硅、贫铁、高钾、低钠特点。
- By complementing the equivalent oxide thickness (EOT) of a 1.7nm nitride/oxynitride (N/O) stack gate dielectric (EOT=1.7nm) with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. 在国内首次将等效氧化层厚度为1·7nm的N/O叠层栅介质技术与W/Ti N金属栅电极技术结合起来;用于栅长为亚100nm的金属栅CMOS器件的制备.