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- half clock cycle 半时钟周期
- Each machine cycle takes 12 oscillator or clock cycles. 每个机器周期为12个振荡器或时钟周期。
- Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. 翻译：存取外部SRAM比存取内部SRAM每个字节要额外多一个时钟周期。
- This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. 这意味这那几个烦人的汇编指令的执行也需要额外的一个时钟周期。
- Godson 2 E. pipelined instructions every clock cycle from four decoding instructions, Dynamic and fired five full pipeline of functional components. 龙芯2E的指 令流水线每个时钟周期取四条指令进行译码，并且动态地发射到五个全流水的功能部件 中。
- The circuit is verified through stimulation and processes a complete chroma format 4:2:0 macroblock data in 293 clock cycle. 该滤波器经过仿真验证,对一个完整的4:2:0格式的宏块数据进行环路滤波仅需293个时钟周期。
- What CCK does is to apply sophisticated mathematical formulas to the DSSS codes,permitting the codes to represent a greater volume of information per clock cycle. CCK所做的工作是把复杂的数学公式应用于DSSS代码，以允许该代码在每个时钟周期表示更多的信息。
- Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle. 另一个独特的构架特性是内存系统,它允许一个取指,并在同一时间,每一个核可以读取数据在每一个单独的时钟周期内。
- ILP (Instruction-Level Parallelism) is a technologyto enhance the processor performance by increasing the number ofinstructions executed per clock cycle. 指令级并行处理ILP（Instruction-Level Parallelism）是一项增强处理器性能的技术，它通过增加每个时钟周期执行的指令条数而提高性能。
- What CCK does is to apply sophisticated mathematical formulas to the DSSS codes, permitting the codes to represent a greater volume of information per clock cycle. CCK所做的工作是把复杂的数学公式应用于DSSS代码，以允许该代码在每个时钟周期表示更多的信息。
- What CCK does is to apply sophisticated mathematical formulas to the DSSS codes, permitting the codes to represent a greater volume of information per clock cycle . CCK所做的工作是把复杂的数学公式应用于DSSS代码，以允许该代码在每个时钟周期表示更多的信息。
- These objective functions were considered efficient before since the latencies of interconnects were within single clock cycle or even could be neglected. 由于过去晶片内部连线的延迟所需要的时间是可以忽略的，这样的方程式被认为是足够的。
- All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. 所有的寄存器都直接与算逻单元(ALU)相连接,使得一条指令可以在一个时钟周期内同时访问两个独立的寄存器。
- Timing Violation Error : RST on instance tx_tb1_tf_tf.uut.nnt1_DCM_INST must be asserted for 3 CLKIN clock cycles. 按我的理解，这是要求DCM的RST信号必须保持3个CLKIN的时钟周期。可是我将RST信号延长至3个时钟周期后，仍然有这个告警。
- I apportioned half the property to each of them. 我把财产的一半分配给他们各人。
- This item specifies the number of clock cycles needed after a bank active command before a precharge can occur. 此项介绍在刷新前,激活指令需要的时钟周期。
- She reckoned she had cut her cost by half. 她估计她减少了一半的费用。
- I worried half the night and have a fitful sleep. 我半个晚上都一直在担心，故而时醒时睡。
- For example, if the sample event is clock cycles and the sampling interval is set to 10,000,000 then performance data is collected after every 10 million clock cycles. 例如,如果样本事件为时钟周期数,取样间隔设置为10,000,000,则每隔一千万个时钟周期收集一次性能数据。
