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- After study a series array multipliers algorithms and architectures, . the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill. 本文研究讨论了各种不同阵列乘法器的结构和原理,并完成了在门电路级设计了32位基4Booth编码并采用42压缩的Wallace高性能阵列乘法器电路。
- This thesis has accomplished the design of register transfer level (RTL) of every unit in the digital processing module, and passed function verification, logic synthesis, and gate level verification. 本文完成了数字处理模块各个单元的寄存器传输级(RTL)设计,并通过了功能仿真、逻辑综合与门级仿真。
- The one gripe I do have with the Quest is in the level design. 我确实有寻求有的一报怨在水平内设计。
- The design includes system level design, RTL level design and logic synthesis . 设计工作包括系统级设计、RTL级设计、逻辑综合。
- The verification includes RTL simulation, gate level simulation and static timing analysis. 验证工作包括RTL级仿真、门级仿真和静态时序分析。
- Finally and some discussions are made on the advantages and disadvantages of the Gate Level Evolvable Hardware. 在函数级进化中,首先在FPGA内部设计了用高级功能模块和互连矩阵构成函数级进化的结构,探讨了如何利用这种结构缩短染色体编码并设计了用于函数级进化的系统平台。
- This flow could use the gated clock,the operand isolation and the gate level optimization to decrease the power consumption without changing the original design. 这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗。
- Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping. 高级综合结果中常量元件和输出悬空端口导致门级工艺映射结果中存在显式冗余。
- You will learn about level design, how to model, texture and light scenes and props. 了解各种质地、场景、道具等等设计要求;
- The Bad Drab level design Monotonous combat Aliens are constantly recycled, dull to look at, boring to fight. 缺点:升级系统很单调;战斗很无聊;敌人类型重复;画面惨淡,没有战斗欲望。
- A new method of the system level design for measurability is introduced in this paper. 摘要介绍了一种新颖的系统级可测试性设计策略。
- In order to improve the security of the system, the breakers are operated to control the power of the sluices in the dynamoelectric method and the gate level gauge is composed of absolute Gray coder and elastic equilibrium sensor. 为了提高系统的安全性 ,采用了电动操作断路器对闸门的动力电源进行控制。 闸位计采用绝对值格雷码编码器以及弹性平衡传感器组成。
- Architecture: Design how the backlog items will be implemented. This phase includes system architecture modification and high level design. 体系架构阶段:构思如何实现待定项。本阶段包括系统架构修改和高层设计。
- "It provides a high level design for a thorough optimizer, code generator, scheduler and register allocator for a generic modern RISC processor. 作者在编译器的实践方面经验丰富,主要关注如何选择编译技术,技术的工程实现以及如何对技术进行改进。
- Architecture is a "universal and conception" description of command automation system from the point of top level design. 体系结构是从顶层设计的角度,对指挥自动化系统进行的一种"统一的和概念的"描述。
- Base on IC technological level, this paper introduce the cross-talk's influence on nanometer level design and solution to it. 针对目前集成电路工艺水平的特点,简要介绍了串扰对纳米级设计的影响以及解决方案。
- Job description: - High level design - Project Management - Bridge SE Job requirement: - Be able to stay in Japa...... ... 公司名称:陕西众信超达科技有限公司工作地点:陕西省西安市发布时间:2009-4-11
- In order to simplify the design flow of an application specific integrated circuit, the system level design issue is getting more important. 为了简化晶片设计的流程,系统层级设计因此变的更加重要。
- A man appeared at the castle gate in the guise of a woodcutter. 一个男子打扮成樵夫的模样出现在城堡的门口。
- gate level combinational circuits [计] 门级组合电路