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- In this paper, a solution to fractional frequency dividing frequency synthesizer is introduced. 文中介绍了一种小数分频频率合成器的设计方案。
- N is the desired noninteger frequency divider. N为所要求的非整数分频值。
- A phase-lock circuit composed of special phase-lock CMOS chip CD 4046 and frequency dividing chip CD 4040 is designed,with a simple external integral loop filter composed of a resistance and a capacitance. 用CMOS专用数字锁相芯片CD4046(内部集成有鉴相器和压控振荡器)和分频芯片CD4040构成了实际锁相电路,外加由电阻和电容形成的简单的片外积分环路滤波器。
- It was used as a frequency divider and no numbers are decoded from it. 它被用作无解码输出的分频器。
- Verilog HDL design of frequency divider in RTC module is studied here. 文中研究在RTC模块中分频器设计的Verilog HDL实现。
- digital frequency dividing circuit 数字式分频电路
- This paper gives out a design of the equal duty ratio arbitrary integer frequency divider based on FPGA. 给出了一种基于FPGA的等占空比任意整数分频电路的设计方法。
- Describes a new design of pulse frequency dividers in which timers NE556 and sequencecontrol unijunction transistors are used. 利用定时器NE556和程控单结晶体管，设计了一种新型多路脉冲分配器。
- Additionally, a highly precise coder on the shaft is researched.A simple and effective frequency divider is designed for correlative calculation. 此外，文中还对高精度码盘在伺服系统中的应用展开了深入的研究，并设计了一套简单实用的分频器以便进行相关的运算。
- The key building blocks in the frequency synthesizer are the voltage controlled oscillator (VCO) and the high frequency divider circuit. 摘要:压控振荡器与除频器是频率合成器电路中，主要的电路之一。
- A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider. 摘要提出了一种基于共振隧穿二极管的新型边沿触发D触发器并将之用于构成二进制分频器。
- In the case of a transponder utilizing FDM (Frequency Divided Multi-access) mode, a Linearizer installed in the transponder may be employed to reduce cross modulation distortion. 在一个转发器,利用差分(频分多址)方式,一个装有转发器线性可以减少调制失真。
- Other than VCO, the frequency divider is the design bottleneck for high-frequency PLL since the conventional flip-flop based structure is not suitable for high-speed operation. 除压控振荡器外，除频器是另一实现高频锁相迴路之设计瓶颈。
- He varied the transmission frequency. 他变换了无线电传送的频率。
- This thesis presents two voltage controlled oscillators and four injection locked frequency dividers, which are implemented by using standard TSMC and UMC 0.18um CMOS process respectively. 摘要:此论文提出了二个压控振荡器和四个注入锁定除频器，它们分别使用了标准台积电0.;18微米和联电0
- Voltage controlled oscillator (VCO) and frequency divider (FD) are the main components of phase locked loop (PLL). For VCO, low phase noise can avoid the affection of Adjacent-Channel Interference. 摘要:压控振荡器与除频器是锁相迴路中，主要的电路之一。对压控振荡器而言，低相位杂讯可避免造成相邻通道的干扰。
- A unit of frequency equal to one cycle per second. 赫兹频率的单位，等于每秒一周
- This thesis presents one voltage controlled oscillator and two injection locked frequency dividers, which are implemented by using standard TSMC 0.18um and 0.35um CMOS process respectively. 摘要:此论文提出了一个压控振荡器和二个注入锁定除频器，它们分别使用了标准台积电0.;18微米和0
- This paper introduces the principle of the frequency division and presents the circuit design of the decimal frequency divider based on FPGA. The VHDL language is used for the programming. 摘要介绍了一种基于FPGA的小数分频器的分频原理及电路设计，并用VHDL进行编程实现，并对这种小数分频器的抖动进行分析和计算。
