- EDAC,TMR and CFC were implemented in VHDL on FPGA.
- EDAC, TMR and CFC were implemented in VHDL on FPGA.
- The designing process of the EDAC circuit is described in the paper.
- To alleviating the effect caused by SEU, we use software based EDAC to guarantee the integrity of the memory system.
- O-SP was activated with CDAP,bound to TT with ADH as a spacer,EDAC as condensation reagent.
- The ABP treated with EDAC can be replaced by the surrounding tissues and has good biocompatibility.