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- The Improvement of Digital Loop Filter of Interface in APDH 对光纤环路接入网接口数字滤波器的改良
- digital loop filter 数字环路滤波器
- The invention discloses a hardware device of an AVS-based loop filter and a hardware implementation method, belonging to the field of digital audio/video coding and decoding technique. 本发明公开了一种基于AVS的环路滤波器的硬件装置以及硬件实现方法，涉及数字音视频编解码技术领域。
- In chapter two, it discusses the algorithm of deblocking loop filter in H.264/AVC and AVS respectively. 264/AVC和AVS标准中的去块效应环路滤波;
- Both incorporation exterior VCO and loop filter could rattling realize celerity Phase Lock function. 结合外部VCO和环路滤波器可以很好的实现快速锁相功能。
- The method of designing the loop filter with the phase margin and loop bandwidth is displayed. 并提出了从环路带宽和相位余量出发设计环路滤波器的方法。
- At last,the loop filter is also analyzed and contrived taking account of effection of additional phase shift by the sampling-holder. 考虑到取样保持器的附加相移影响，对环路滤波器进行了分析和设计。
- However, the chargepump is usually followed by a passive loop filter that integrates the chargepump output current to a VCO control voltage. 电荷泵通常后接一个用于积分电荷泵输出电流的无源环路滤波器去形成VCO的控制电压。
- In this paper, according to the arithmetic of loop filter in AVS audio video coding standard, a high effective loop filter circuit is designed. 根据AVS音视频编码标准中提出的环路滤波算法设计了一个高效的环路滤波器。
- For the case without considering delay, comparisons of our results with that by generic PI form loop filter design are made. 在不考虑时间延迟因素的情形，将本论文所提出的PI形式滤波器设计，与一般的设计作比较。
- We introduce a symmetric feedback circuit onto a “bootstrapping” charge pump with a typical second order loop filter to improve jitter performance. 首先在此锁相迴路运用一个对称式回授电路在一“提靴架构”电荷帮浦，搭配一个典型的二阶低通滤波器来增进相位抖动的特性。
- The phase noise of the design plan of DRO +PLL has been analyzed. The loop filter has been designed for PLL with CAD. The frequency synthesizer in X-band has been designed. 同时,本文还分析了DRO 稳频锁相设计方案的相位噪声指标,利用软件对锁相环的环路滤波器进行了设计,研制了X 波段的点频锁相源。
- universal digital loop transceiver 通用数字环路发送接收器
- As an example, the application of National Semiconductor PLL IC LMX2315 is introduced in this paper which includes loop filter design and its registers configuration. 文中以国家半导体公司的LMX2315为例介绍集成锁相环芯片的应用，包括环路滤波器设计和相关寄存器配置。
- digital loop carrier multiplexer 数字环路载波复用设备
- The PLL part, made of PD, Loop Filter, Voltage Control Oscillator, is the key circuit of the system to produce steady and continuous frequency scanning signal. PLL锁相环路部分主要由鉴相器、环路滤波器、电压控制振荡器构成，产生稳定连续的频率扫描信号，它是本系统的关键电路。
- A phase-lock circuit composed of special phase-lock CMOS chip CD 4046 and frequency dividing chip CD 4040 is designed,with a simple external integral loop filter composed of a resistance and a capacitance. 用CMOS专用数字锁相芯片CD4046(内部集成有鉴相器和压控振荡器)和分频芯片CD4040构成了实际锁相电路,外加由电阻和电容形成的简单的片外积分环路滤波器。
- The PLL (phase lock loop) is realized by form of charge pump, its loop filter is passive two-order LPF. Compared to other form of active filter, this CP PLL has less noise, which does some good to its output spectrum. 微波锁相环采用电荷泵的形式,其环路滤波器为无源二阶低通滤波器,相比采用有源滤波器的锁相环,它不会附加有源噪声,而且滤波器结构简单,便于调试。
- Integrated Kalman filter is used estimations of INS's error and GPS receiver clock's error.It is used code tracking loop in order to function of loop filter in tradition code tracking loop. 在该算法中，组合卡尔曼滤波器除完成INS误差及GPS接收机时钟误差的估计外，还参与了GPS码跟踪，即完成传统码跟踪环中环路滤波器的功能。
