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- The realization of a combinational logic circuit simulation platform with Applet technology of Java 2 is introduced in this paper. 介绍了以Java 2标准中的Applet技术开发组合逻辑电路网络仿真实验平台的原理.
- To improve the speed and efficiency of combinational logic circuit design, this paper presented a Game Genetic Algorithm (GGA). 为了有效提高组合逻辑电路进化设计的速度和效率，提出了一种基于博弈遗传算法的电路进化设计算法。
- Multiplexer is a kind of combinational logic circuit, which can be selected an in-put datum among several data and sent it to out-put port. 数据选择器是一种能从多个输入数据中有选择地将一个输入数据送到输出端的组合逻辑电路。
- To improve the speed and efficiency of combinational logic circuit design, this paper presented a Game Genetic Algorithm (GGA).In GGA, each output of the circuit was regarded as a player. 摘要为了有效提高组合逻辑电路进化设计的速度和效率，提出了一种基于博弈遗传算法的电路进化设计算法。
- Design Basis of Combinational Logic Circuit 组合逻辑电路设计基础
- The Design of MSI Combinational Logic Circuit MSI组合逻辑设计
- combinational logic circuit designing 组合电路设计
- The Application of Data Selector in the Combinational Logic Circuit 数据选择器在组合逻辑电路中的应用
- Using Java to Realize the Combinational Logic Circuit Simulation Platform 用Java实现组合逻辑电路仿真平台
- Computer aided logical design(CALD) software design rapidly and exactly combinational logical and sequential logical circuits. 该软件可以快速、准确、可靠地设计出多输入多输出液控逻辑回路，设计结果可以达到最优。
- The method of judge and remove in the phenomenon of race and hazard of the combinational logic circuit 组合逻辑电路中的竞争冒险现象的判断和消除
- It can give BDD presentation of Boolean function or arbitrary combination logic circuits which are presented by CDL, and can realize different operation of Boolean function by the operation to BDD. 能完成对任意基于CDL语言描述的组合逻辑电路或布尔函数，实现其BDD表示并通过对BDD的操作实现对相应组合电路或布尔函数的操作。
- The number of inputs available to a given logic circuit. 扇入，输入可在逻辑电路得到的输入端数目
- A combinational logic element having at least one input channel. 一种至少有一个输入通道的组合逻辑元件。
- Simplifying the Design of Combinational Logical Circuit with Eprom 用EPROM简化组合逻辑电路的设计
- Usually, the abbreviation for logic circuit. 通常是“逻辑电路”的简写。
- Usually,the abbreviation for logic circuit. 通常是“逻辑电路”的简写。
- The research of multi-fault test generation for combinational logic circuits 组合逻辑电路多故障测试生成算法的研究
- Research on Netlist Optimization of Asynchronous Combinational Logic Circuits 异步组合电路网表优化的研究
- Discuss the way of communal technique to design combinational logic circuits 公用技术组合逻辑电路设计方法的初步探讨
