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- A combinational logic element having at least one input channel. 一种至少有一个输入通道的组合逻辑元件。
- Because of the decentralization,a large-scale logic array and ASIC digital circuit can realize the CMAC controller easily. 由于采用分散CMAC结构，简化了控制器实现的复杂度，易于采用大规模可编程数字逻辑阵列和ASIC数字电路予以硬件实现。
- A clock Network is combinational logic between a clock source and the registers in the transitive fanout of the source. 时钟网络：网络是一个时钟之间的时钟源和源寄存器传递扇组合逻辑。
- Field programmable logic array, FPGA, can reduce the NRE cost, design risk Time-to-Market and maintenance cost of electronic system.So FPGA is widely used in electronic systems. 现场可编程门阵列（FPGA）能够减少电子系统的开发风险和开发成本，缩短上市时间，降低维护升级成本，故广泛地应用在电子系统中。
- The realization of a combinational logic circuit simulation platform with Applet technology of Java 2 is introduced in this paper. 介绍了以Java 2标准中的Applet技术开发组合逻辑电路网络仿真实验平台的原理.
- To improve the speed and efficiency of combinational logic circuit design, this paper presented a Game Genetic Algorithm (GGA). 为了有效提高组合逻辑电路进化设计的速度和效率，提出了一种基于博弈遗传算法的电路进化设计算法。
- Multiplexer is a kind of combinational logic circuit, which can be selected an in-put datum among several data and sent it to out-put port. 数据选择器是一种能从多个输入数据中有选择地将一个输入数据送到输出端的组合逻辑电路。
- In this paper a method of a combinational logic B/BCD converosin Jor any BCD code is investigated, And some example are given to illustra-te the use of the method. 本文以几种常用的BCD码为例;深入研究任意BCD码的B/BCD转换的组合逻辑变换网络.
- Network configuration of separated Crossbar employs the SEED devices as high speed optical modulators and the FET SEED device integrated on a single GaAs chip as optical logic array. 该体系结构中可采用自电光效应（SEED）器件作为高速光调制器，采用在单块GaAs基片上集成的场效应晶体管－自电光效应器件（FET－SEED）作为逻辑光开关器件。
- FPGA, Field programmable logic array, can reduce the NRE cost, design risk, Time-to-Market and maintenance cost of electronic system.Therefore, FPGA is widely used in electronic systems. 现场可编程门阵列（FPGA）能够减少电子系统的开发风险和开发成本，缩短 上市时间，降低维护升级成本，故广泛地应用在电子系统中。
- By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis. 提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ;重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 .;此方法有效地利用了已有的成熟技术;为缩短 RTL综合的开发时间提供了一种有效途径
- In designing auto-control devices including computer, apart from the combinational logic design, the now fairly popular method which attracts daily increasing attention is the microprogramming. 设计包括计算机在内的自动控制装置,除采用组合逻辑设计方法外,目前比较流行、且愈来愈为人们重视的方法,是微程序设计方法。
- To improve the speed and efficiency of combinational logic circuit design, this paper presented a Game Genetic Algorithm (GGA).In GGA, each output of the circuit was regarded as a player. 摘要为了有效提高组合逻辑电路进化设计的速度和效率，提出了一种基于博弈遗传算法的电路进化设计算法。
- FPLA Field Programmable Logic Array 现场可编程逻辑阵列
- autonomous testable programmable logic array 独立可测的可编程序逻辑阵列
- bipolar programmable logic array 双极型可编程逻辑阵列
- Computer aided logical design(CALD) software design rapidly and exactly combinational logical and sequential logical circuits. 该软件可以快速、准确、可靠地设计出多输入多输出液控逻辑回路，设计结果可以达到最优。
- rewritable programmable logic array 可重写可编程逻辑阵列
- iterate logic array testing method 迭代逻辑阵列测试法
- At this point your logic is at fault. 在这一点上你的推理是错误的。
