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- clock pulse oscillator 时钟脉冲振荡器
- Trigger control circuit from complex programmable logic device (CPLD), ICL7135CN, the clock pulse circuit and optocoupler inverter constituted. 触发控制电路由复杂可编程逻辑器件（CPLD）,ICL7135CN,时钟脉冲电路、反相器和光耦构成。
- The harmonic balance simulation and envelope simulation are applied in the CAD progress of pulse oscillator, the results of simulation are listed, and the output signal of pulse oscillator is analyzed by mathematical method. 以脉冲振荡器的cad为例，对脉冲振荡器分别进行谐波平衡仿真和包络仿真，列出了仿真结果，并对脉冲振荡器输出信号进行数学分析。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时，（或者在最后一个时钟脉冲的下降沿之后）主机将时钟拉低，键盘/鼠标不必重新传输任何数据。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/ mouse does not need to retransmit any data. 如果在第一个高->时钟跳变时，（者在最后一个时钟脉冲的下降沿之后）机将时钟拉低，键盘/标不必重新传输任何数据。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the a last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时，（或者在最后一个时钟脉冲的下降沿之后）主机将时钟拉低，键盘/鼠标不必重新传输任何数据。
- The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register. 触发器的并行加载可以是同步的（即在时钟脉冲到达时发生）或异步的（不依赖于时钟），这取决于移位寄存器的设计。
- ratchet magnetic pulse oscillator 磁性脉冲振荡器
- Envelope Simulation of Pulse Oscillator 脉冲振荡器的包络仿真
- fractional order neural-type pulse oscillator 分数阶神经型脉冲振荡器
- A microprocessor designer may decide to make all instructions last five clock pulses. 微处理机设计人员可以决定使所有的指令持续五个时钟脉冲。
- hysteretie neural-type pulse oscillator 滞迟神经型脉冲振荡器
- Note that a set of lights attached to O1, O2, O3 would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse. 注意，一组接在O1,O2,O3上的灯泡将以二进制（模8）形式显示第一个脉冲以来已完成的完整时钟脉冲数。
- In binary synchronous communication, the use of clock pulses to control synchron ization of data and control characters. 在二进制位同步通信中,使用时钟脉冲来控制数据和控制字符的同步。
- Programmable output clock pulse width 输出脉冲宽度可编程
- suppressed clock pulse duration modulation 压缩时钟脉冲宽度调制
- To get the current temperature, you must write 35 fixed bytes into the port register.The sensor expects 16 clock pulses on the SCK line while the SS# is low. 为了取得当前温度;你必须写35个固定的字节到端口寄存器.;当ss低的时候，该传感器预计16个时钟脉冲在串行时钟线。
- multiphase clock pulse generator 多相时钟脉冲发生器
- I didn't wake up until I heard the alarm clock. 直到听到闹钟的铃声我才醒来。
- That clock is a family heirloom. 那个座钟是祖传下来的。
