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- Dai Hongyu, Zhou Runde. A sinusoidal power clock generation circuit for energy recovery logic. Microe-lectronics, 34(2004)1, 71 8722;76, (in Chinese). 戴宏宇;周润德.;用于能量回收逻辑的正弦功率时钟电路
- A Clock Generation Circuit in LCD Driver and Controller LCD驱动控制时钟电路的设计
- A Clock Generation Circuit with Tunable Frequency Range 一种频率可调时钟产生电路的研究
- Design and Implementation of Clock Generation Circuit in Gigabit Ethernet Chip 千兆以太网卡芯片时钟产生电路的设计与实现
- A Sinusoidal Power Clock Generation Circuit for Energy Recovery Logic 用于能量回收逻辑的正弦功率时钟电路
- This thesis presents the CMOS design and implementation of the low noise amplifier (LNA) and clock generator circuits, the most critical parts of the analog front end in a UWB transceiver. 本论文探讨使用CMOS制程设计与实现两个位于超宽频接收机类比前端最重要的电路，分别为低杂讯放大器与时脉产生器电路。
- Energy Recovery Threshold Logic and Power Clock Generation Circuits 能量回收阈值逻辑及其功率时钟产生电路
- clock generation circuit 时钟产生电路
- Secondly, we present all the circuit modules of the develop system, which include power module, FPGA configuration module, clock generation module, video in/out module, RS232 serial port module, Ethernet interface and USB interface module and so on. 第二部分重点讲述了基于FPGA的MPEG-4芯片开发系统各个电路模块的设计，包括电源模块、FPGA配置模块、时钟生成模块、视频输入/输出模块、RS232串口模块、以太网接口模块、USB接口模块等。 同时也介绍了I~2C总线控制器的FPGA实现以及USB接口的实现。
- Here, we use a DLL-based clock generator with nonoverlapping circuit to generate three nonoverlapping phases used for capacitor error-averaging in pipelined ADC. 在本论文中，我们利用延迟锁相迴路加上相位非重叠电路来实现一个三相非重叠电路，以供给管线式电容平均容错之类比数位转换器。
- Figure 4-7 depicts a general circuit for testing capacitor leakage. 图4-7是测试电容器漏电的一般电路。
- The whole AFE circuit includes a bias circuit, a clock generator, a chopper stabilization amplifier, a post-amplifier, and a second-order continues-time low-pass filter. 本文所提整体类比前端电路包含偏压电路、时脉产生器、截波稳定型放大器、后置放大器、和二阶连续时间低通滤波器。
- Through keyboard and code generation circuit, coding and pulse modulation vibration with infrared project to form infrared project circuit. 通过键盘及代码生成电路、编码、脉冲调制振荡和红外发射构成红外发射电路。
- Revisable high voltage driving waveform generation circuit is designed, 2.Data storage and control circuit is designed. 3. 2、设计制作了可编辑的高压驱动波形产生电路，产生波形、时间参数、能量恢复时间参数等实时调节的高压驱动波形。
- Analog Devices offers ultra-low jitter clock distribution and clock generation products for wireless infrastructure, instrumentation, broadband, ATE and other applications demanding sub picosecond performance. ADI公司提供超低抖动时钟分配集成电路(IC)和时钟发生IC,用于无线基础设施、仪器仪表、宽带、自动测试设备(ATE)和其它要求亚皮秒性能的应用。
- The ADC aperture jitter must be minimal, and the sampling clock generated from a low phase-noise quartz crystal oscillator. ADC的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。
- Finally,using the novel architecture and algorithm,an example of power generation circuit applied in ultra high frequency(UHF) passive transponder integrated circuit(IC) is given. 然后基于提出的电路结构和算法;给出了特高频无源电子标签电源产生电路的设计实例.
- Finally, the experimental data for the LNA and the clock generator prototypes are presented to demonstrate the functionalities and performances of the proposed circuit architectures. 最后，本论文呈现低杂讯放大器与时脉产生器电路晶片的量测结果，藉以验证所提出电路架构的弁鄐峈穛{。
- Can be used in the synthesis loop vibration, high-precision clock generator and FSK / / 3PSK modulation. 可用于本振合成回路，高精度时钟发生器和FSK／／3PSK调制。
- And finally, a clock generator based on the 3rd order CPPLL is fully designed with UMC 0.25 CMOS process. 最后，采用UMC 0.;25 CMOS工艺技术设计了一个用作时钟产生的三阶电荷泵锁相环。
