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- Dai Hongyu, Zhou Runde. A sinusoidal power clock generation circuit for energy recovery logic. Microe-lectronics, 34(2004)1, 71 8722;76, (in Chinese). 戴宏宇;周润德.;用于能量回收逻辑的正弦功率时钟电路
- Analog Devices offers ultra-low jitter clock distribution and clock generation products for wireless infrastructure, instrumentation, broadband, ATE and other applications demanding sub picosecond performance. ADI公司提供超低抖动时钟分配集成电路(IC)和时钟发生IC,用于无线基础设施、仪器仪表、宽带、自动测试设备(ATE)和其它要求亚皮秒性能的应用。
- Secondly, we present all the circuit modules of the develop system, which include power module, FPGA configuration module, clock generation module, video in/out module, RS232 serial port module, Ethernet interface and USB interface module and so on. 第二部分重点讲述了基于FPGA的MPEG-4芯片开发系统各个电路模块的设计，包括电源模块、FPGA配置模块、时钟生成模块、视频输入/输出模块、RS232串口模块、以太网接口模块、USB接口模块等。 同时也介绍了I~2C总线控制器的FPGA实现以及USB接口的实现。
- The ADC aperture jitter must be minimal, and the sampling clock generated from a low phase-noise quartz crystal oscillator. ADC的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。
- Can be used in the synthesis loop vibration, high-precision clock generator and FSK / / 3PSK modulation. 可用于本振合成回路，高精度时钟发生器和FSK／／3PSK调制。
- And finally, a clock generator based on the 3rd order CPPLL is fully designed with UMC 0.25 CMOS process. 最后，采用UMC 0.;25 CMOS工艺技术设计了一个用作时钟产生的三阶电荷泵锁相环。
- Reference Clock Generation for Sampled Data Systems 如何产生数据采集系统的参考时钟
- In chapter two, a three nonoverlapping phases clock generator is presented at first and the experimental results are given finally. 在第二章中，一各三相非重叠电路将会被提出，而其实验结果将会被论述在本章之末。
- The Research of Digital Clock Generation 数字时钟信号产生技术的研究
- The dissertation describes the principle of spread spectrum clock generator and its implement structure.Especially analyzes PLL and the loop divider. 本文先介绍了扩谱时钟发生器（SSCG）的基本原理以及扩谱时钟的不同实现电路结构，并对扩谱时钟发生器中的锁相环（PLL）以及环路分频器进行了分析。
- Here, we use a DLL-based clock generator with nonoverlapping circuit to generate three nonoverlapping phases used for capacitor error-averaging in pipelined ADC. 在本论文中，我们利用延迟锁相迴路加上相位非重叠电路来实现一个三相非重叠电路，以供给管线式电容平均容错之类比数位转换器。
- The whole AFE circuit includes a bias circuit, a clock generator, a chopper stabilization amplifier, a post-amplifier, and a second-order continues-time low-pass filter. 本文所提整体类比前端电路包含偏压电路、时脉产生器、截波稳定型放大器、后置放大器、和二阶连续时间低通滤波器。
- First, in order to analyze the PLL clock generator, we have established the loop parameters.The parameters effect on the PLL transient characteristic has been studied. 首先，为了分析锁相迴路时脉产生器，我们建立了迴路的参数并探讨这些参数对锁相迴路暂态响应的影响。
- True visionaries are often misunderstood by their own generation. 真正有远见卓识的人往往招致同时代人的误解。
- I didn't wake up until I heard the alarm clock. 直到听到闹钟的铃声我才醒来。
- That clock is a family heirloom. 那个座钟是祖传下来的。
- I set it by the clock on the railway station. 我是按火车站的大钟对的。
- The clock ticks louder and louder in a quiet room. 钟的滴答声在静静的房间里变得越来越响。
- The grandfather clock was back in its old place. 落地式大摆钟已放回原处了。
- There is a generation gap between my parents and I. 我父母和我之间有代沟。
