您要查找的是不是：
- instruction cache miss rate 指令缓存缺失率
- cache miss rate 超高速缓存故障率
- When u see mages having a lower melee miss rate. 当你看到法师的近战命中率远低于你的。
- Indicates that the request is treated as a cache miss and the page is executed. 指示将请求当作缓存未命中处理并执行该页。
- The item is evicted from the cache and the request is handled as a cache miss. 从该缓存中收回项并将请求当作缓存未命中处理。
- It seems like some sort of cache miss effect, but that does not make sense to me given the actual memory of the system. 看上去就象是高速缓存丢失的影响,但根据系统的实际内存它不会对于我有任何意义。
- Remember, the kernel invokes the AVC and the AVC invokes the security server if there is a cache miss. 记住,如果未击中缓存,那么核心调用AVC,AVC调用安全性服务器。
- An instruction cache miss will occur when fetching this instruction, resulting in the fetching of the modified instruction from storage. 当取这个指令时会发生指令高速缓存失败,结果就会从存储器中取得修改后的指令。
- In SQL Server 2005, when there is no cache insert after a cache miss, only an SP: CacheMiss event is written to the trace. 在SQL Server 2005中,如果在缓存未命中之后没有插入缓存,则只将SP:CacheMiss事件写入跟踪。
- These actions can cause cache misses and page faults. 这些操作可能导致缓存未命中和页错误。
- Because when large page is used, TLB(translation lookaside buffer) can map much larger virtual memory area,which leads to the reduction of miss rate. 但是通常用来处理有关军事,气象,经济等方面海量计算量应用程序,频繁的切换导致了计算性能的低下。
- Consequently, users can expect to see a reduced number of events reported for multiple cache miss events that occur for a single stored procedure or function. 因此,对于为单个存储过程或函数所发生的多个缓存未命中事件,用户可以看到对这些事件所报告的事件数有所减少。
- Dual Wielding vs Two Handed WeaponsThere's arguments for both. The damage output is pretty similar overall due to the miss rate of the offhand of a dual wielder. 双手挥舞vs双手武器对两者的选择是有争议的。因为存在双持的命中惩罚,所以输出的伤害大体上是差不多的。
- We use TDT3 corpus as test corpus. The best tracker achieves 4.0% miss rate and 1.8% false alarm. The tracking cost is 0.0029 and Norm(C_(track))is 0.1239. 本文选用TDT3语料作为测试语料;系统达到最好的追踪性能时;在漏报率为4.;0%25的情况下;误报率仅为1
- The next time, the portal access control component requests this information, there will be a cache miss, and the most current information is read from the portal configuration database. 当门户访问控制组件下一次请求这一信息时,将有缓存丢失,并且最新的信息是从门户配置数据库中读取的。
- Based on PKUnity network computer platform, this paper analyzes the d-TLB miss rate and performance penalty of many typical applications under different d-TLB structures and page sizes. 本文基于北大众志网络计算机平台,详细分析了d-TLB结构和页面大小等配置参数的变化,对典型应用程序d-TLB失效率和d-TLB失效导致的性能损失等所产生的影响。
- Total number of cache misses against the in-memory cache after the service started. 服务启动后在内存缓存中未命中缓存的总数。
- The testing result of SPEC95 indicates that the miss rate of the BTB with 256 entries is 12.7%, while the BTB with 4K entries is 7.3%. Moreover, as for their prediction accuracy of branch instruction, both of them can reach 90%. SPEC95测试结果表明：本文所设计的256项和4K项BTB的命中失效率分别为12.;7%25和7
- The OCP replacement policy results in plain cache behaviors,and makes cache misses analyzing and optimizing easily and efficiently. OCP Cache替换策略简化了Cache行为和Cache失效分析方法。
- At this rate we won't be able to afford a holiday. 照这样下去，我们不会有时间／钱去度假的。
