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- bit synchronous clock signal 位同步时钟信号
- The invention relates to a method and device for generating synchronous clock signals for writing operation in disk drive. 本发明涉及在磁盘驱动器中产生用于写操作的同步时钟信号的方法和装置。
- A New Technique for Rapid Picking- up Bit Synchronous Clock in Digital Communication 一种位同步时钟提取方案及实现
- The device always generates the clock signal. 时钟信号总是由设备端生成的。
- For synchronous connections, where a clock signal is needed, either an external device or one of the DTEs must generate the clock signal. 为了达到同步的连线，需要有时钟讯号才行，有可能是一台外部设备或者其中一台资料终端设备必须产生时钟讯号。
- The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal. 你的微型计算机执行程序的速度将与你的时钟信号的速度成线性关系。
- The transition from voltage to no voltage is referred to as the trailing edge of a clock signal. 电感从一定值下降到0值的跃迁叫做时钟信号的后沿。
- Design and Realization of Embedded Synchronization Clock System. 嵌入式同步时钟系统的设计与实现。
- The system can hold the 'clock' signal inactive to inhibit the next transmission. 系统拉低时钟线,将禁止下一次传输。
- DDR SDRAM is a high speed and largecapacity memory,but because of the need of synchronous clock and the characteristic that it is controlled by control command,there must be a controller between the system and DDR SDRAM. DDR SDRAM是一种大容量,高速度的同步动态存储器,但是由于其对同步性的要求以及需要由控制字来控制的特点使得他与系统之间必须有一个接口来实现时钟同步和对DDR SDRAM进行控制。
- To demodulate GMSK signal,DSP is used in receiver to achieve error spectrum estimation,bit synchronization recovery and decode. 为了实现GMSK信号解调，接收机中DSP实现了调制信号的误差频谱估计、位同步恢复及译码。
- When the device detects this state, it will begin generating Clock signals and clock in eight data bits and one stop bit. 当设备检测到这个状态,它将开始产生时钟信号
- This paper discusses the advantages of PLD (programmable logical device) in designing a digital circuit,and at the same time,discusses how to realize a 6 bit synchronous up/down counter with clear by using PLD GAL16V8. 介绍了PLD器件在设计数字电路时的优越性，同时叙述了以PLD器件GAL16V8实现六位可清零、可置数的同步可逆计数器的原理。
- The CODEC can be used to carry on coding transmission and decoding reception in parallel with code error detection and bit synchronized signal recovering. 该编译码器能进行并行发送编码和接收译码,并带有误码检测和位同步提取的功能。
- The key difference between these two is that the DCE device provides the clock signal for the communications on the bus. 这两种类型之间的主要差异是DCE装置在汇流排上提供通讯使用的时脉信号。
- Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accom-plished by an external clock signal. 它的功能是当感应到输入电压界限时提供一个锁存开关，通过外部时钟信号完成复位。
- The clock signal with precise duty cycle produced by DCM is used in the bus data DDR transmission.The simulation results are also given. 利用DCM产生的具有精确占空比的时钟信号,给出了其在DDR总线数据传输中的应用,并给出了仿真结果。
- Realization of Bit Synchronous Signal Recovery Digital Circuits 位同步信号恢复的数字电路实现
- Thus, the clock signal passing between the FPGA and the ADC's for each channel will physically clock in this frequency range. 这样，FPGA和AD转换器之间的时钟频率物理上落于这个频率窗口之内。
- A method of realizing clock signal by CPLD during GPS desynchronization.Automation of Electric Power Systems,2003,27(17):64-67. GPS失步后时钟信号的CPLD实现方法.;电力系统自动化;2003;27(17):64-67
