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- The device always generates the clock signal. 時鐘信號總是由設備端生成的。
- The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal. 你的微型計算機執行程序的速度將與你的時鐘信號的速度成線性關係。
- The transition from voltage to no voltage is referred to as the trailing edge of a clock signal. 電感從一定值下降到0值的躍遷叫做時鐘信號的后沿。
- The system can hold the 'clock' signal inactive to inhibit the next transmission. 系統拉低時鐘線,將禁止下一次傳輸。
- The key difference between these two is that the DCE device provides the clock signal for the communications on the bus. 這兩種類型之間的主要差異是DCE裝置在匯流排上提供通訊使用的時脈信號。
- Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accom-plished by an external clock signal. 它的功能是當感應到輸入電壓界限時提供一個鎖存開關，通過外部時鐘信號完成複位。
- The clock signal with precise duty cycle produced by DCM is used in the bus data DDR transmission.The simulation results are also given. 利用DCM產生的具有精確占空比的時鐘信號,給出了其在DDR匯流排數據傳輸中的應用,並給出了模擬結果。
- Thus, the clock signal passing between the FPGA and the ADC's for each channel will physically clock in this frequency range. 這樣，FPGA和AD轉換器之間的時鐘頻率物理上落於這個頻率窗口之內。
- For synchronous connections, where a clock signal is needed, either an external device or one of the DTEs must generate the clock signal. 為了達到同步的連線，需要有時鐘訊號才行，有可能是一台外部設備或者其中一台資料終端設備必須產生時鐘訊號。
- A method of realizing clock signal by CPLD during GPS desynchronization.Automation of Electric Power Systems,2003,27(17):64-67. GPS失步后時鐘信號的CPLD實現方法.;電力系統自動化;2003;27(17):64-67
- Intensity and pulsewidth of incident signal, the length of dispersion shift fiber (DSF) and walk off between incident and clock signal influenced the output clock intensively. 重點分析了色散位移光纖的長度和入射信號的脈寬和強度、以及走離對輸出時鐘信號的影響;
- The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. 轉換過程和數據採集過程通過CS和串列時鐘信號進行控制,從而為器件與微處理器或DSP輕鬆介面創造了條件。
- Time clock signal source directly fetches from clock signal of PCI bus in the computer system or signal generator, which can generates high frequency time clock signal. 該時鐘信號源直接取自於該電腦系統中PCI匯流排的時鐘信號或是一可產生高頻時鐘信號的時鐘信號產生器，用以供應該計數電路所需的輸入時鐘信號。
- Serial transmission over long distance requires that the timing information for the receiver be transmitted together with the data so that a separate clock signal is not required. 由於接受者需要定時信息，長距離的串列傳輸為了避免單獨傳時鐘信號需要把定時信息和數據一起傳輸。
- The control signals for the ac-excitation must be non-overlapping clock signals. 控制信號為交流勵磁時必須不能重複時鐘信號。
- The principle of the method is to introduce a clock isolation circuit which tracks clock transitions just like a clock signal, yet isolates the clock from the 「clock-used-as-data」 logic. 主要的方式是導入時鐘隔離電路追蹤時鐘轉換如時鐘訊號，然後"時鐘做為資料"邏輯做為隔離時鐘技術。
- System included a PLL synthesizer, mixers, filters, amplifiers, attenuators, and a clock signal generator.According to the requirement of the input and output, each part is analyzed and proved. 系統主要包含頻率合成器、混頻器、濾波器、放大器、衰減器、時鐘模塊等部件，根據系統輸入、輸出的要求，本論文依據相應的指標對各個模塊進行了分析和論證。
- The disease is still in its primary stage. 這疾病仍然在初發階段。
- When the device detects this state, it will begin generating Clock signals and clock in eight data bits and one stop bit. 當設備檢測到這個狀態,它將開始產生時鐘信號
- The invention relates to a method and device for generating synchronous clock signals for writing operation in disk drive. 本發明涉及在磁碟驅動器中產生用於寫操作的同步時鐘信號的方法和裝置。
