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- 非同步FIFO的FPGA實現Asynchronous FIFO Implementation Using FPGA
- 基於FPGA非同步FIFO的研究與實現Research and Implementation of Asynchronous FIFO Based on FPGA
- 一款低功耗非同步FIFO的設計與實現Design and Realization of a Low Power Asynchronous FIFO
- LMS演算法的FPGA實現是自適應天線陣用於實踐的關鍵之一。FPGA-based implementation of LMS algorithm is one of the key techniques in the application of adaptive array antennas.
- 實現to achieve
- 非同步FIFOasynchronous FIFO
- 基於金字塔結構編碼的8點離散小波變換及其逆變換的FPGA實現研究FPGA Implementation Research on 8 Samples DWT and IDWT of Pyramidal Structural Data Coding
- 基於DSP和FIFO的多路高速數據採集系統在PFN中的應用The Application of a Multi-channel High Speed Data Acquisition System Based on DSP Plus FIFO in PFN
- 在而試過程中,經常被問及的問題之一就是如何計算一個FIFO的深度。One of the most common questions in interviews is how to calculate the depth of a FIFO.
- 基於FPGA的非同步FIFO設計Asynchronous FIFO Design Based on FPGA
- 非同步FIFO中存儲單元的分析設計Analysis and Design of Memory Cell of Asynchronous FIFO
- 混沌跳頻序列發生器的FPGA實現FPGA Realization of a Chaotic FH Sequence Generator
- 系統處理的是連續視頻信號,數據量大,採樣頻率高,本文採用了一種利用FIFO的幀中斯管理方法來解決視頻信號的採集問題。The sampling rate of continuous video data processed by the system is high ,so we use a method by the use of FIFO frame buffer to capture the video.
- 非同步FIFO在實時圖像匹配處理機中的應用Asynchronous FIFO and its application in real-time image matching system
- 根據該方案,使用FPGA實現了基於CORDIC演算法的數字檢波器。On the basis of this,we propose the design scheme of digital detector based on CORDIC algorithm.
- 讀寫數據寬度不同的非同步FIFO設計Asynchronous FIFO Design with Different Data Width between Reading and Writing
- 語言進行描述。基於分散式演算法的高階FIR濾波器及其FPGA實現High Order FIR Filter Based on Distributed Arithmetic and Its FPGA
- 本文從實際應用出發,研究了橢圓曲線密碼體制演算法的FPGA的實現;In this paper, we study the implementation of the ECC algorithm by the FPGA from practical aspect.
- IS-95碼分多址系統上行通道接收機捕獲單元的設計及FPGA實現The Design and FPGA Realization of the Capture Unit in Uplink Channel Receiver of IS 95 CDMA Cellular System
- 傳統的非同步FIFO設計採用同步讀寫地址后比較產生空滿標誌的方法,面積大、工作頻率低。Traditional FIFO design often synchronizes write/read address first,then compares them to generate empty/full signals.