and the results of experimentation based on FPGA show that the test approach reduces dynamic power consumption by an average of 15.282% and 12.21% for the two adders respectively.

 
  • 基于FPGA的实验结果表明,对于8位行波进位加法器,该方法将电路的平均动态功耗降低了15.;282%25,对于16位超前进位加法器,则降低了12
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