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- Design of all digital phase locked loop based on VHDL 基于VHDL的全数字锁相环的设计
- Embedded Fast All Digital Phase Locked Loop with Automatic Modulus Control 嵌入式自动变模控制的快速全数字锁相环
- ADPLL(All Digital Phase Locked Loop) ADPLL（全数字锁相环）
- all digital phase locked loop 全数字锁相环
- TMS320F240 DSP is used to realize the digital Phase Locked Loop(PLL) and real-ize the hot-swap function of the parallel system. 采用TMS320F240型DSP芯片实现数字锁相同步,实现并联系统的热插拔功能。
- This paper discusses a method to demodulate FSK signal, on the basis of FPGA chip, by applying all- digital phase locked loop. 本文研究了一种采用全数字锁相环实现频移键控FSK信号解调的新方案。
- Several blocks such as ELST, CRC coder/decoder, Bit synchronousdigital phaselocked loop and jitter attenuate digital phase locked loop aredescribed in detail. 论文对作者所设计实现的部分模块作了较为详细的介绍，包括弹性存储器的设计和CRC编解码的设计以及位同步数字锁相环和抖动衰减锁相环的设计。
- After the signals treated by a digital phase locked loop of zero phase-difference when phase and frequency following,this problem has satisfactorily been solved. 采用对相位和频率跟踪无相差的数字锁相环对同步信号进行处理可满意地解决上述问题。
- The normal idea to make up a digital controled oscillator (DCO)of the digital phase locked loop (DPLL)is to delete the pulses unwanted It need that the master clock frequency must be more faster than the output frepuency of the DPLL. 传统的数字锁相环 (DPLL)多采用吞脉冲的方法来实现DCO ,此方法要求工作频率远高于DPLL的输出频率。
- In order to realize the frequency and phase of output voltage synchronized with input voltage when UPS works, in the paper, a digital phase locked loop based on MCU with high precision is presented. 为了实现不问断电源(UPS)运行时输入输出电压频率和相位保持一致,本文结合锁相环的原理,利用单片机实现高精度的数字锁相环。
- Design of Digital Phase Locked Loop Based on VHDL 基于VHDL语言的数字锁相环的设计与实现
- DSP based Digital Phase Locked Loop for Inverter 基于DSP的逆变器数字锁相技术
- digital phase locked loop (DPLL) 数字锁相环
- all digital phase - locked loop 全数字锁相环
- The Design of Digital Phase Lock Loop for Inverter Based on FPGA 基于FPGA的逆变器全数字锁相环设计
- The Signal Processing Method of Coriolis Mass Flowmeter Based on A Digital Phase Locked Loop 基于数字锁相环的科氏质量流量计信号处理方法
- Design and implementation of wide-lock range digital phase locked loop base on FPGA 宽频带数字锁相环设计及基于FPGA的实现
- One example is the phase comparator of a phase locked loop. 一个例子是相锁环状态下的相位比较器。
- Relational Digital Phase Lock Loop slot synchronizer for PPM Laser Communication System PPM光通信相关式数字锁相环时隙同步器
- all - digital phase - locked loop (ADPLL) 全数字锁相环
