ADPLL

 
       
  • 全数字锁相环

ADPLL的用法和样例:

例句

  1. This thesis proposes a new digital controlled oscillator (DCO) and a new phase frequency detector (PFD) architecture for the all digital phase-locked loop (ADPLL) with low power design.
    本论文提出一个新的数位控制频率振荡器及一个新的相位频率侦测器之架构以设计一个低功率的全数位式锁相迴路。
  2. ADPLL(All Digital Phase Locked Loop)
    ADPLL(全数字锁相环)
  3. The results of the simulation show that ADPLL can lock the frequency timely and effectively, and is has many advantages such as follow rate rapidness;high precision;
    仿真结果表明,ADPLL能够及时有效地进行频率锁定,具有控制跟踪速度快、精度高、可调性强及捕获频带宽等优点。

ADPLL的海词问答与网友补充:

提问补充

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