A Low-power Design Methodology Clock-gating

 
       
  • 门控时钟的低功耗设计技术

A Low-power Design Methodology Clock-gating的用法和样例:

例句

  1. A Low Power Design of DSP Processor Bus
    一种降低DSP芯片总线功耗的设计方案
  2. A Low power Design of PDP Drving Waveform
    一种低功耗的PDP驱动波形设计
  3. Adaptive Clock Gating Technique for Low Power IP Core Design in SoC
    应用于片上系统中低功耗IP核设计的自适应门控时钟技术
  4. In this paper a low power 2D DCT/IDCT processor is presented.
    设计了一种低功耗的2D DCT/IDCT处理器。
  5. Described was a design of a serial real-time clock chip with I2C bus interfaces,which was a low power,full binary-coded decimal(BCD) clock/calendar chip,and whose address and data were transferred serially through an I2C bidirectional bus.
    论述了一种采用I2C总线接口的串行实时时钟芯片的设计方法.

A Low-power Design Methodology Clock-gating的海词问答与网友补充:

提问补充

A Low-power Design Methodology Clock-gating的相关资料:

临近单词

目录
应用 附录 查词历史
    更多>>今日热词