A Low-power Design Methodology Clock-gating的用法和样例：
- A Low Power Design of DSP Processor Bus
- A Low power Design of PDP Drving Waveform
- Adaptive Clock Gating Technique for Low Power IP Core Design in SoC
- In this paper a low power 2D DCT/IDCT processor is presented.
- Described was a design of a serial real-time clock chip with I2C bus interfaces,which was a low power,full binary-coded decimal(BCD) clock/calendar chip,and whose address and data were transferred serially through an I2C bidirectional bus.