Using a modern development technology of DSP(DSP Builder) implementation for example,the FPGA design,which was verified in the digital signal process circuit of an 16-order FIR filter was mainly presented.

• 提出了一种采用DSP Builder实现有限冲激响应滤波器的设计方案,并以一个16阶低通FIR数字滤波器的实现为例,设计并完成软硬件仿真与验证。 结果表明,该方法简单易行,能满足设计要求。