This design has been implemnted on a milion-gate scale ASIC chip, which has been integrated on a SONET packet-processing system, and provided data queueing management to 5Gbps traffic over 2 OC48 channels.

• 该设计方案实现于一颗百万门级的ASIC 芯片上,并集成于一个SONET上对分组数据包的分类、监控以及统计计费系统中,提供了对两路OC48 光网络上5Gbps 数据流量的数据队列管理服务。