This architecture is developed from aparallel VLSI architecture for FS. Moreover, function modules of 2SS motionestimation are set off. And they are designed, implemented and simulated with VerilogHDL, ISE and Modelsim on Spartan-IIE XC2S300e FPGA chips.

• 本文对已有的用于全搜索算法实现的VLSI结构进行了改进,设计了符合二步搜索算法要求的FPGA实现结构,并在对其理论分析之后,对实现该算法的运动估计模块进行了功能模块的划分,并运用Verilog HDL硬件描述语言、ISE及Modelsim开发工具在Spartan-IIE XC2S300e FPGA芯片上完成了对各功能模块的设计、实现与时序仿真。